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Hold violation on multicycle path...........................

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hahtesham

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Can a multicycle path violate Hold?? Here is what exactly in my mind.
There can be a multicyle due to a large combination logic path between start flop and end flop or there could be a flop between start flop and end flop.

Now in the first case,where there is purely combinational logic between the two flops,is there any chance of hold violation...????

In the second case the hold may violate on the intermediate flop.
 

hahtesham said:
Now in the first case,where there is purely combinational logic between the two flops,is there any chance of hold violation...????
.
Click to expand...
The delay is one thing, clock skew is another. Deep combinational paths don't make the path immune from hold viols if clock skew is large.
Also, depends on what behavior you expect on the said path in the application.
 
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Agree with lostinxlation!

Another point is : not all the multicycle path contain many conbination logic on data path.
Someone may specify the multicycle path for some special requirement.
For example, multi-frequency design, Source Syncronous Bus design.
In that case, you should be careful about the hold violation in the multicycle path.
 
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