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To understand Verilog primitives...

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mashhur

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Hello everybody,

could somebody explain me this situation please?

/* Module */
HTML: 
module my_module(I/Os);
 // some statements
end my_module;
/* Testbench */
HTML: 
module tsbnch();
initial
begin
  $monitor();
  $finish;
end
 //instance my_module
  my_module utt(args);
end tsbnch;

here my question goes. in initial statement we used $finish before getting instance of my_module, does it stop program? for ex. in C++ if u use exit(), a program stops to execute.
And does $monitor() display if the variable changes its value after $monitor() statement?

thanks in advance.
 

My suggestion is to try it by yourself and see what happens. If you have a question on the result, we'd help.
 

I debugged it myself. When I start a program the debugger goes directly to $finish state but doesn't stop if I step in (F11 in ISim).
I think that it is wrong, cuz $finish is equal to exit() function in C if I am not wrong...

Thanks!
 

try something like this:
#1000 $finish;

it should be more interesting after toggling some signals

link
 

It doesn't really matter that $finish is before the instantiation of "my_module" Each "begin" block will execute once per simulation, but you don't have any code in your begin block, and just as important, no simulation time statements, so your sim will end instantly. Try putting some code after "begin" and some time delay, as lincoln2 shows above.
 
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