how to calculate effective capacitance at node of circuit?

Currently i am using the Cadence Virtuoso(180nm) and spectre simulator....
i have to calculate the capacitance at the node of circuit where some of sources of MOSFET and drains of other MOSFETs are connected(as i have to calculate the energy comsumption = V*V*C).
So How can i calculate the Capacitance?

I am not sure about the question though ,but i'll giveit a shot :
1. I did a few theory questions a while back where in i'd use a std formula of number of Gates (yes gates, not particularly MOSFETs) are connected to that node . if u know the applied Vdd (or Vdda ) , the maximum frequency of Gate signal operations (height frequency in that circuit), and avg capacitance per gate u could find the Power by P =V^2 * frequency*Capacitance .

2. When u extract your Layout using "capall" , shouldn't you get the Capacitance values at every node too ?

sarad_kath said:

How can i calculate the Capacitance?

Click to expand...

See this answer and that thread.

If you are looking for dynamic power in vanilla CMOS,
bet that CVVf is far from the whole story. Shoot-through
current is likely much worse.

Forget calculating it.

If you want to get at the various components of IDD,
put voltage sources between drivers and loads (gates)
and in the vdd/vss legs of drivers as well. The integral
abs(I(gate)) across a cycle is your CVV charge. The
difference of I(vss) and I(gate), I(vdd) and I)gate)
per edge, is what the simple calculation ignores and it
can be much greater especially at light loading.

If you want to know what's going on, "instrument it
up" and dope it out. Theory gets you less than halfway.

Trying to answer :: How to calculate the Capacitance at a node?

Click to expand...

For more accuracy you should be having Layout ready.
When you are talking about capacitance two things play role -
1. interconnect parasitic-cap,
2. caps inside device-terminals [ which is captured inside device models, and that is also function of device geometry, voltage, temp etc. ].
For MOS device Source and Drain, parameters like AS, [area of source], AD [area of drain] are used to calculate source/drain area-capacitance, and PS [source-perimeter], PD [drain-perimeter] are used to calculate fringe capacitance; and these capacitors are of reverse junction depletion diode, which forms underneath source & drain, the depletion layer width is voltage dependent and so on.

Do parasitic extraction of the interconnects, with MOS devices having AS, AD, PS, PD & NRD NRS parameters added - during extraction [ some are extracted during LVS some during RC extraction ]. During RC extraction, capacitance can be extracted / netlisted either as lumped or coupled. If power is the only concern - lumped cap extraction should be fine.
Run simulation on the post layout netlist. And yes what erikl said, captab analysis - which is not a separate or independent one - it can be enabled for dc & tran [? i forgot]

hi fren...with reference to" how to calculated the capacitance of node on the circuit?" i have attached the circuit(cmos in cadence) too...for easyness. I hope it will be helpful to get the answer. pls check the link for circuit.

https://obrazki.elektroda.pl/45_1294480074.jpg

Thanks to all for my responding my questions.....i have found the "captab analysis " in the spectre for both transient and dc analysis...which gives the capacitance at every node of given schematic...................But i still need to consult the book that gives the capacitance analysis of digital circuit like cmos inverter, cmos nand ...full adder...etc. based on SPICE Model....So Guys would you please give some books to read on this(capacitance analysis)???

i dont have any specific book in mind, but one good book for CMOS VLSI is
1. CMOS VLIS Design , A circuits and Systems Prespective by Neil Weste and David Harris

2. Digital Integrated circuits, a design prespective 2nd Edition (i forgot the author) - quite exhaustivly covers for inter transistor parasitics. A ton of theory in this one.