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verification design flow

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paavithra

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Difference between verification, testing, and post-silicon validation.
 

https://www.eecs.berkeley.edu/~sseshia/pubdir/postSi-dac10.pdf

---------- Post added at 10:19 ---------- Previous post was at 10:17 ----------

Testing is the process of checking the functionality of each module mostly at system level.

Testing can also be done design level,module level, unit level, integration of modules, system. There are suitable tools for ths same.

you can refer this link where they have many pdf files. something may be useful to you.

**broken link removed**
 
Testing is to check the chip functionality when chip after tape-out using ATE!
Verification is to check the chip functionality when chip before tape-out using simulation!
 

What I know about the verification is functional level. It test your design functionality. However, for testing, it doesn't nothing to do with your original purpose. Instead, it's to test whether the die or chip is intact after taped out. In other words, it's physical level for checking out aborting in taped out process.
 
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