Config 74ACT161 right or not?

I am a newbie in digital circuits. I want to do a divider-by-N with Fairchild 74ACT161 counter, who can tell me my configuration is right or not?
I want to change the resistors to get different N for dividing.

The output should be Q3. But I don't know how to connect TC/Q0/Q1/Q2?

I haven't played with counter/dividers like these for many years I'm afraid.

I'll have a go though...

Start by clearing all your connections.

Then
Connect 3V3 to pin 16 as usual.
Connect pin 8 to ground as usual.

Feed your chosen CLK input to CP (pin2).

Pins 7, 10 and 1 should be tied to 3V3

Connect output Q3 (pin11) to pin 9 via a logic inverter chip eg 74AC04 gate (Edit see final edit below as I think this connection might be wrong!)

Then the chip will show an output that is something like the CLK divided by 16-N where N is the preload count programmed onto pins 3, 4, 5 and 6.

So playing with the logic levels on 3,4,5,6 will affect your division ratio

Hope this helps!

If it doesn't then I'd have to simulate it and play around.
Maybe someone else knows ?

---------- Post added at 02:07 ---------- Previous post was at 01:54 ----------

Actually, I think you might be supposed to connect the inverter in betweeen pin 15 and pin 9. I really can't be sure. You then get the divided output from pin 15.




Therefore do it this way:

Connect 3V3 to pin 16 as usual.
Connect pin 8 to ground as usual.

Feed your chosen CLK input to CP (pin2).

Pins 7, 10 and 1 should be tied to 3V3

Connect output pin15 to pin 9 via a logic inverter chip eg 74AC04 gate

Then the chip will show an output that is something like the CLK divided by 16-N where N is the preload count programmed onto pins 3, 4, 5 and 6.

So playing with the logic levels on 3,4,5,6 will affect your division ratio
You then get the divided output from pin 15.


I'm not really a digital guru I'm afraid. However, note that I don't think you are meant to run ACT series at 3V3.

Thank you very much, G0HZU.
Actually, I have a file "divide by N using the 161 counter". That show how to coonect 160, not 161. So I am not sure how to config 161.
According to the file, the output should be Q3/Pin11, not TC/Pin15. I think your suggestion about pin15 connecting pin9 is right.
But I don't know which is output?
Anyway, that seems not improtant, I will try to buy IC and breadboard to try.

The HC160 & HC161 are virtually identical - the HC160 is a BCD rather than binary counter so the circuit should be fine.

I have simulated it and it looks ok. The parallel load is 5 in my example so the counter counts 11 pulses (= 16 - 5).

Keith.

Glad it appears to work. Basically it is a divide by 16 counter but you preload it so it starts partway through the count (start point set by pins 3,4,5,6)

So each time it gets to 16 you need to reload the corrent start point again. You have to flip the logic sense to the load pin 9 to get it to work.

Also, it migh be worth using a spare 74AC04 inverter ahead of the CLK input pin 2 just to make sure you feed this chip with a nice square waveform.

I don't know what this chip is like for jitter or phase noise but hopefully it should be OK.

Thank all of you very much. The jitter or phase noise is not strict.

I designed the circuits and found that the circuits is NOT stable. The sch file includes two part. 1st part use 74AC04 to form TTL from sinwave, the high level is about 3.4V, and the low level is about 0V.
The input sinwave is 60M/+15dBm. And 74AC04 pin1 waveform is good and smooth, but pin2 have some distortion. And pin4 become worse and have many flips.
The 74AC04 pin4 linked to 74ACT161 pin2, and the output is NOT stable.
I hope to get any divide ratio from the circuits.
XXX denots NULL. And the Vdd=+3.3V.

1. Is 74AC04 too slow to handle 60M?
2. Why is not stable?