2 stage simple CMOS opamp that gives 1 MHz bandwidth with 60 degree PM, gain of 50db

Please any one help me. I want to make this circuit on cadence. I want to dram a simple CMOS opamp that gives 1MHz bandwidth with 60 degree Phase margin gain at 50 DB and load capacitance of 1PF
Please help me to draw this circuit. I have already study basic CMOS but dont have exact idea

Hello umair9926,

First of all,since you have already studied about basic concepts of CMOS OpAmp,then the next step is to choose the circuit topology that will implement your amplifier.I suppose that the OpAmp you are designing is for academic/training purposes and not straightly intended for production,so starting with the design of the classical 2-Stage CMOS OpAmp (1st Stage-->Diff Pair with active loads & 2nd Stage-->CMOS inverter) would be a good idea.Now,you need some good tutorial that will get you in the design procedure.I would suggest that you read the following two books at the section of the Operational Amplifiers :

1.CMOS Analog Circuit Design (Allen,Holberg)
2.Design of Analog Integrated Circuits and Systems (Laker,Sansen)

and of course perform a google search for more resources like :

**broken link removed**

Finally,after having acquired a good level of OpAmp design knowledge at theoritical level (based on first order equations mainly) you will apply all these on cadence spectre environment and via simulations with try & error method you will try to converge to a solution for the set of specifications you have.

Make a start up and if you feel that you need more info and help come back with precise questions.

Good Luck!

Regards,
Jimito13

I have done one lab of op-amp in my lecture. I think it is hard to design one to meet that requirement. But I think that depends on more requirements, Such as the supply voltage, swing range of output, the process, power etc.

To be honest, I do not have any idea about the phase margin about the op-amp. maybe some can give me some indication on that.

Actually designing such an Opamp is quite easy, as long as you follow a few basic rules. A 75 dB gain and a 1MHz bandwidth can be achieved without much effort

First of all, don't choose random W/L transistors sizes. Take the NMOS differentail pair, for example: if the current mirrors has a W/L=1 than the input transistors must have W/L=0.5 because the current flowing through them is half of the current flowing through the current mirror.


Same thing for the load transistors: the PMOS W/L=0.5*0.3=1.5, current is the same flowing through the NMOS input transistors but you must compensate for decreased channel conductivity (thats why it is multiplied by 3).

Do the same stuff for the output stage, but in this case W/L PMOS = 6*W/L NMOS

The absolute W/L values will have a minor impact on performance as long as the ratios are respected.

The phase margin compensation is easy too: a 1k resistor and a 100nF capacitor should do the job, if not increase cap to 1 pF