4bit adder using vhdl error 10500

hi every one
i have a problem in compiling 4bit adder using vhdl in quartus 2


Library ieee;
Use ieee.std_logic_1164.all;

Entity 4bitadder is -- it is showing error here
Port
(
I0,I1 : in STD_LOGIC_VECTOR(3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR(3 downto 0);
Cout : out STD_LOGIC
);
End 4bitadder;

Architecture arch of 4bitadder is -- it is showing error

Component fulladder
Port
(
A,B,Cin : in std_logic;
S,Cout : out std_logic
);
End component;

Signal Temp : STD_LOGIC_VECTOR(2 downto 0);

begin

FA1: fulladder port map
(
A => I0(0),
B => I1(0),
Cin => Cin,
S => S(0),
Cout => Temp(0)
);

FA2: fulladder port map
(
A => I0(1),
B => I1(1),
Cin => Temp(0),
S => S(1),
Cout => Temp(1)
);

FA3: Fulladder port map
(
A => I0(2),
B => I1(2),
Cin => Temp(1),
S => S(2),
Cout => Temp(2)
);

FA4: fulladder port map
(
A => I0(3),
B => I1(3),
Cin => Temp(2),
S => S(3),
Cout => Cout
);

End arch;
wheather i have to include 1 bit adder in this or as an another file when using component instantiation please tell me that
my errors are


Error (10500): VHDL syntax error at 4bitadder.vhd(4) near text "4"; expecting an identifier

Error (10500): VHDL syntax error at 4bitadder.vhd(14) near text "4"; expecting an identifier
please help me as soon as possible.

Hello,

Try to change the name of your entity/archi. I'm not sure but I would say VHDL doesn't like identifiers starting with a digit...

Regards,
Franck.

VHDL identifiers must start with a letter.

Hi,

Here is the rules that applies with VHDL identifiers :

Identifiers are used both as names for VHDL objects, procedures, functions, processes, design entities, etc., and as reserved words. There are two classes of identifiers: basic identifiers and extended identifiers.
The basic identifiers are used for naming all named entities in VHDL. They can be of any length, provided that the whole identifier is written in one line of code. Reserved words cannot be used as basic identifiers (see reserved words for complete list of reserved words). Underscores are significant characters in an identifier and basic identifiers may contain underscores, but it is not allowed to place an underscore as a first or last character of an identifier. Moreover, two underscores side by side are not allowed as well. Underscores are significant characters in an identifier.

The extended identifiers were included in VHDL '93 in order to make the code more compatible with tools which make use of extended identifiers. The extended identifiers are braced between two backslash characters. They may contain any graphic character (including spaces and non-ASCII characters), as well as reserved words. If a backslash is to be used as one of the graphic characters of an extended literal, it must be doubled. Upper- and lower-case letters are distinguished in extended literals.

Important notes:

• A basic identifier must begin with a letter.
  
• No spaces are allowed in basic identifiers.
  
• Basic identifiers are not case sensitive, i.e. upper- and lower-case letters are considered identical.
  
• Basic identifiers consist of Latin letters (a..z), underscores ( _ ) and digits (0..9). It is not allowed to use any special characters here, including non-Latin (language-specific) letters.

thank you all for ur help