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How to make a supply voltage is 1.8V circuit works well with supply voltage at 0.7V

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enchanter

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I designed a simple hand shake circuit which ic working well at 1.8V supply voltage. Now I have to make it working with 0.7V supply voltage. It needs more than 50ns to stable status from power on. One of the RS flip flop output start at 0.4V around and goes to High (0.7V) for quite a long time. After that the circuit work well as it at 1.8V supply voltage.

So my question is how could I shorten the start time from power on to stable status? (there's no capacitor components in the circuits, the output only drive on or to NORs or INVERTERs. ).

Thanks.
 

Hi, I think for your circute to work properly it has to be from 0.7 because the ic's you are using has their own minimum triggering voltages but you can also refers to the datasheets of the chips for more info.
 

Thanks for you reply. But I am design the circuit with CMOS transistors. So I have no datasheet to look for.
 

enchanter said:
Thanks for you reply. But I am design the circuit with CMOS transistors. So I have no datasheet to look for.
Click to expand...

What process are you using?1.8V is 0.18 um process. If that is the only process you have then you simply cannot make it work.
 

iterativeend said:
1.8V is 0.18 um process. If that is the only process you have then you simply cannot make it work.
Click to expand...
If your foundry supports native and/or low-threshold transistors, this is of course possible, e.g. Alice Wang's FFT Processor, a chip which works down to 180mV, and which was fabricated in 2003 using a standard 0.18µm CMOS logic (!) process. See that chip and a short description in this (scroll down). You'll find some more low voltage 0.18µm chips there.
Here's a literature reference on this topic.
 

forward body biasing and subthreshold operation with optimized for that circuitry might help to work with 0.7V supply
 

The process is based on TSMC 0.18. The Vth is 0.5. The function of the circuit from simulation is correct. But just need more time to make it stable from power on.

But the bias solution, does it mean I have to change the bulk connect (currently it is connect to GND) to a negative supply voltage?
 

forward biasing means, that you have to open slightly (say 0.3...0.5V)a correspondent P/N junctions,- i.e. for PMOS bulk should be lower than Vdd, for NMOS bulk should be higher Gnd (it is possible for triple well process option). Such biasing will reduce MOSFETs thresholds, by price of increasing leakage of course. And it is necessary to have bias generators, that will keep an appropriate biasing conditions across PVT.
 

attachments might help
 

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  • 6.3.B.pdf
    5.1 MB · Views: 92
Thanks a lot. I will study it carefully.
 

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