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How variables differ from signals ?

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kalaiyarasan

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variables are used only inside the process statement

signal are used both inside and outside process statements.

so how variable differs from signal or in what aspect it differs ... in memory or processing speed.

instead of creating variable if i m creating a signal what will happen
 

sigal and variable

variables are updated immediatly
Signals are updated on the next delta cycle.

so, if you look at the following process:

Code: 
signal a,b : std_logic;


process(clk)
  variable c,d : std_logic;
begin
  if rising_edge(clk) then
    
    a <= ip;
    b <= a;
    op1 <= b;
    
    c := ip;
    d := c;
    op2 <= d;
    
  end if;
end process;

In this process, op1 is connected to the input via 3 pipeline registers.

For op2, the pipeline length is only 1 register, because c and d only represent a wire as they are updated immediatly.

Now, to confuse you:

Code: 
signal a,b : std_logic;


process(clk)
  variable c,d : std_logic;
begin
  if rising_edge(clk) then
    
    a <= ip;
    b <= a;
    op1 <= b;
    

    op2 <= d;
    d := c;
    c := ip;

  end if;
end process;

Here, both op1 and op2 show an input to output connection of 3 registers.


In a simulator, variables use a lot less memory as signals have to store current value, future value and when to apply the value. Here is an example

a <= '1', '0' after 10ns;

This needs to store '1' now and the fact that at time = 10ns it changes to '0'.

A variable only stores current value.
 
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