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Switch Design of Current Steering DAC?

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winsonpku

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current steering dac

Hi All,
Due to the charge injection and clock feedthrough, the switch will generate very large current glitch during the low to high or high to low transition of the switch for the current steering DAC. For example, the current source is 32uA, but the switch will generate about 300uA current glitch during the transition of the switch.
How much the current glitch will degrade the performance of the DAC and how to reduce the current glitch?
Thanks!
 

current steering

winsonpku said:
how to reduce the current glitch?
Thanks!
Click to expand...

Standard method is to use a compensation MOSFET with W/2, s. e.g. the LOW_POWER...PDF below, pp. 69 ff (or intrinsic pp 34 ff).

A more sophisticated method is the "bottom plate sampling", s. e.g. the Uni-KL_ADC...pdf, p. 13

HTH! erikl
 

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  • uni-kl_adc-review_jan03_5782.pdf
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current switch for dac

Hi Erik
Really appreciate for you help.
For your experience, how much the influnce the current glitch on the performance of dac? Thanks!

Best regagrds,
Winson

erikl said:
winsonpku said:
how to reduce the current glitch?
Thanks!
Click to expand...

Standard method is to use a compensation MOSFET with W/2, s. e.g. the LOW_POWER...PDF below, pp. 69 ff (or intrinsic pp 34 ff).

A more sophisticated method is the "bottom plate sampling", s. e.g. the Uni-KL_ADC...pdf, p. 13

HTH! erikl
Click to expand...
 

how to reduce dac glitch

winsonpku said:
For your experience, how much the influnce the current glitch on the performance of dac
Click to expand...
Hi Winson,
this depends on your system; it can't be estimated without considering the whole system incl. its timing. Suggest to simulate it!
Cheers, erikl
 

glitch dac

The architecture of my DAC is current steering.
I think the timing of my DAC is OK, at least the function is right,
but i simulated the DAC, the performance is so bad and i found maybe only the current glitch is the main reason.
Could you give any advice? Thanks!

Best Regards,
Winson
erikl said:
winsonpku said:
For your experience, how much the influnce the current glitch on the performance of dac
Click to expand...
Hi Winson,
this depends on your system; it can't be estimated without considering the whole system incl. its timing. Suggest to simulate it!
Cheers, erikl
Click to expand...
 

current steering dac architecture

winsonpku said:
The architecture of my DAC is current steering.
I think the timing of my DAC is OK, at least the function is right,
but i simulated the DAC, the performance is so bad and i found maybe only the current glitch is the main reason.
Could you give any advice? Thanks!
Best Regards,
Winson
Click to expand...
I'd try and estimate the size of the charge which is introduced by the glitch, and put it into relation to the charge produced by the signal to be measured. By this, you may be able to estimate its influence on the DAC's resolution.

Apart from that, I think your glitch is much too big. You should at least use the W/2 compensation scheme I showed you with my last answer. By this you should be able to cut down the glitch by at least an order of magnitude (depending, ultimately, on the (as good as possible) symmetry of your switch layout).
Cheers, erikl
 

switch for current dac

Hi Erikl,
I think it's very hard to evaluate the charge induced by the glitch.
Up to now, i think the current glitch maybe generated mostly by the clock feed-through.
Anyway, really thanks for your help!
Best Regards,
Winson

erikl said:
winsonpku said:
The architecture of my DAC is current steering.

I'd try and estimate the size of the charge which is introduced by the glitch, and put it into relation to the charge produced by the signal to be measured. By this, you may be able to estimate its influence on the DAC's resolution.

Apart from that, I think your glitch is much too big. You should at least use the W/2 compensation scheme I showed you with my last answer. By this you should be able to cut down the glitch by at least an order of magnitude (depending, ultimately, on the (as good as possible) symmetry of your switch layout).
Cheers, erikl
Click to expand...
Click to expand...
 

In some of my spectre simulations, I found that 2*W deglitching transistors would almost eliminate the problem. The gate must be fed the opposing signal to each line.

I will soon test this idea in a chip but thank you for the thesis which gave me this idea.
 
Back in the day, using NJFETs, we found that source switching
induced less bump than gate switching. You would like to steer
the current with as little voltage perturbation as needed,
especially when settling tails are driving your conversion
rate or accuracy@.
 

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