Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Low noise synchronous digital design (low EMC)

Status
Not open for further replies.
V

vitalik_man

Newbie level 1
Joined
Dec 12, 2008
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,286
Hello! Can anyone suggest a number of rules to observe when designing a low noise synchronous digital circuit at front-end level? E.g. gray counter usage. Back-end design tricks are also welcome (e.g. clock skew control).
 

Gray coding is good. Also use a spread-spectrum PLL to generate the clock if possible. Large, evenly-distributed clock skew helps too. Use lowest voltage possible, and slowest clock speed possible. PCB layout is important too (use a whole ground plane or more than 1 if possible.) Use a hefty power grid and plenty of ground pins. Use decoupling capacitors on the PCB and on the die itself if available. Then shield everything multiple times.

Try this to learn more:
http://www.atmel.com/atmel/acrobat/doc1619.pdf
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top