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It's a method for adjusting the timing of DQ/DM/DQS to account for (and reduce) system-board skew.
Normally, between the PHY and the memory module signals are routed to try to be the same delay (flight time), but of course that's impossible, so there is some skew, which reduces system max performance. One way to reduce skew is to use more expensive multi-layer system PCB. Now with DDR3 there's a cheaper way to try to reduce the skew, by adjusting signal timing at the PHY, and it's called "system-level flight time compensation."
is this the same as write and read leveling ? do we include the pcb routing delays in the delay in the dq/dqs signal delays that goes to each memory device? If so, do we take into consideration the pcb trace delays of cs/ras,cas,we signals as well?
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