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transmission gate problem

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lokesh garg

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i am simulating transmission gate in Hspice using following code....
vcbar 3 0 dc 0v
vc 2 0 dc 1v
vin 1 0 dc 0v
m1 4 2 1 0 N_10_SP w = 0.12u l = 0.08u
m2 1 3 4 2 P_10_SP w = 0.12u l = 0.08u
.lib "L90_SP10" cmos_models
.dc vin -2v 3v 0.001v
.plot dc v(4)
.option post
.probe
.end

i want this gate to be linear for valtages between -1v to 1v... but its not linear at -1v.... how can i get this range... plz help me. i am attaching the simulated output screenshot....
 

It would be a lot easier to see what you are doing if you showed a circuit instead of expecting people to reverse engineer a netlist!

As far as I can see you are powering the circuit off 1V/0V and expecting it to work from -1V to 1V. That doesn't to make sense to me.

Keith.
 

With input below Vtp, the pmos is in cutoff, after which only the nmos is conducting. The reason why the voltage cannot go below -0.9V because the body is forward biased against the source and drain! What is happening is that you have a HUGE current flowing across the forward-biased body-diffusion junction, which clamps the voltage to that of a forward-biased diode!

You should also be taking note of gate-diffusion breakdown issues.
 
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