Debugging Verilog code for calculating the maximum value in an array

UFK · May 26, 2010

Hi
I tried writing a small code to calculate the maximum value in an array. Its as follows:

module max_coef(array,i,mxm);
reg array [0:15];
input integer i;
input mxm;

mxm = array[1];
for (i=0;i<15;i=i+1)
begin
if (array > mxm)
mxm= array;
end
endmodule

Can someone please correct it for me?

Thanks alot.

fcfusion · May 26, 2010

Re: Verilog debugging!

reg array [0:15];

This isn't an array, it's a register. Each position of array can only store 1 bit (0 or 1), not an integer.

Do like this:

integer array [0:15];

or

reg [31:0] array [0:15]

UFK · May 26, 2010

Re: Verilog debugging!

Thankyou fcfusion for your prompt response.
I tried what you suggested. My code now looks like this:

module max_coef(array,i,mxm);
integer array [0];
reg [31] array [0];
input integer i;
input mxm;

mxm = array[1];
for (i=0;i<15;i=i+1)
begin
if (array > mxm)
mxm= array;
end
endmodule

but it gave me the following errors;

ERROR:HDLCompilers:27 - "max_coef.v" line 23 Illegal redeclaration of 'array'
ERROR:HDLCompilers:26 - "max_coef.v" line 24 unexpected token: 'integer'
ERROR:HDLCompilers:26 - "max_coef.v" line 27 unexpected token: '='
ERROR:HDLCompilers:26 - "max_coef.v" line 27 unexpected token: '['
ERROR:HDLCompilers:208 - "max_coef.v" line 21 Port reference 'i' was not declared as input, inout or output
ERROR:HDLCompilers:208 - "max_coef.v" line 21 Port reference 'array' was not declared as input, inout or output
ERROR:HDLCompilers:26 - "max_coef.v" line 27 expecting 'endmodule', found '1'

*sigh* (((((

Added after 49 minutes:

I have another question, if someone can please find a solution to it.

What im trying to do is perform operations on a two dimensional array (representing an image).

I made a coe file and loaded it in my BRAM. To my dissappointment it treated the file as a sequence of numbers n loaded it in a sequential fashion. I hoped to come up with a way to address each memory location co-ordinate wise like x-axis y-axis coordinates so i can manipulate each coefficient. How can that be done?

Can someone please tell me how to make a coe file that can be loaded in two dimensional pattern?

Thanks

fcfusion · May 26, 2010

Re: Verilog debugging!

UFK said:
integer array [0];
reg [31] array [0];

This is wrong. I sugested using one solution or the other, not both. Besides that, the array size is wrong. I sugest using the registers because those are always synthesizable:

reg [31:0] array [0:15]

UFK said:
input integer i;

This is wrong. You can't declare an input has an integer. Besides that, if you receive "i" has an input why do you change it later in the "for" cycle? If you don't need to receive "i" remove it from the inputs and declare it just has a simple integer or register.

And you need a "begin" after "mxm = array[1];" and before the "for" cycle.

Please pay atention to your own code. This is Verilog not C programming. It's a completely different thing. [/quote]

UFK · May 27, 2010

Re: Verilog debugging!

Dear fcfusion

Thankyou for trying to help. Im hopeless at Verilog. thanks anyway

UFK · May 28, 2010

Re: Verilog debugging!

Hii
Im trying to find the maximum value in an array. mxm is supposed to give me the max value at the end.
Please correct the following code for me. Ill be very grateful.

module sample11(b_array,mxm);

input [0:15] b_array;
integer i;
input [0:15] mxm;

assign mxm = 16'h0;

begin
for (i=0;i<15;i=i+1)
begin
if (b_array > mxm)
end
mxm = b_array;
end

endmodule

It gives me the following error:

"sample11.v" line 29 expecting 'endmodule', found 'begin'

fcfusion · May 28, 2010

Re: Verilog debugging!

module sample11(b_array,mxm);

input [0:15] b_array;
integer i;
input [0:15] mxm;

assign mxm = 16'h0;

Either mxm is an input or a wire with a constant assigned, not both. Replace that code for:

module sample11(b_array);

input [0:15] b_array;
integer i;
wire [0:15] mxm;

assign mxm = 16'h0;

Besides that, this code is also wrong:

begin
for (i=0;i<15;i=i+1)
begin
if (b_array > mxm)
end
mxm = b_array;
end

endmodule

You've placed a begin with nothing before. You're forgeting something very important: in Verilog, every code must be controlled by an input signal, generally a clock but you can also use other signals. So, in your module, you must receive a clock has input and then use it to control everything else. This is how it's usually done.

module sample11(clk,b_array,mxm);

input clk; //CLOCK!!!!!

always@(posedge clk) //code will run when clock changes from Low to High
begin
for(....)
begin
...do whatever you want....
end
end

endmodule

Click to expand...

Here is some code for a counter, written by me. You should use it has a template.

`timescale 1ns / 1ps

module counter (clk,reset,counter_out);

input clk;
input reset;
output [13:0] counter_out;

reg [13:0] counter;

assign counter_out=counter;

always @(posedge clk or posedge reset)
begin
if (reset==1) counter<=0;
else if (counter==3999) counter<=0;
else counter<=counter+1;
end

endmodule

Click to expand...

UFK · May 29, 2010

Re: Verilog debugging!

Dear fcfusion

Thankyou very much for helping me yet once again. I did what you suggested i.e. declaring the wire and the clk. Everything worked fine except one error that just wouldnt go away. Then i made some more changes to make it work and now my code looks like this

module maxvalue(b_array);

input [0:15] b_array;
integer i;
reg [0:15] mxm;

initial
begin
mxm = 16'b0;

for (i=0;i<15;i=i+1)
begin
if (b_array > mxm)
mxm = b_array;
end
end

endmodule

Then i tried giving values to b_array in the tb as follows:

module max11_tb();

// Inputs
reg [0:15] b_array;

// Instantiate the Unit Under Test (UUT)
maxvalue uut (
.b_array(b_array)
);

initial begin
// Initialize Inputs
b_array [0]= 13;
b_array [1]= 1;
b_array [2]= 2;
b_array [3]=14;
b_array [4]=12;
b_array [5]=0;
b_array [6]=-1;
b_array [7]=21;
b_array [8]=12;
b_array [9]=2;
b_array [10]=-4;
b_array [11]=0;
b_array [12]=9;
b_array [13]=13;
b_array [14]=10;
b_array [15]=-2;

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

end

endmodule

Click to expand...

It simulates fine but it doesnt give me the results. Do you think you can comment on my code and give me a solution please.
Thanks alot.

fcfusion · May 30, 2010

Re: Verilog debugging!

There is a lot of wrong stuff here and 1 of the errors is mine:
1)

input [0] b_array;

I suggested this but I was wrong, and should be:

reg [31] b_array [0]

This is the correct way and I actually sugested it right in some of my previous posts but then sugested it wrong in my last

2)"Initial" blocks are NOT synthesizable. They are used only for simulation purposes. So use the "always @(posedge clk)" like I sugested. The simulation might still work anyway but that's some really bad coding.

3)

initial begin
// Initialize Inputs
b_array [0]= 13;
b_array [1]= 1;
b_array [2]= 2;
b_array [3]=14;
b_array [4]=12;
b_array [5]=0;
b_array [6]=-1;
b_array [7]=21;
b_array [8]=12;
b_array [9]=2;
b_array [10]=-4;
b_array [11]=0;
b_array [12]=9;
b_array [13]=13;
b_array [14]=10;
b_array [15]=-2;

There are two errors here. First, if you want to initialize the variables do not use "initial". Might still work in simulation though. Use "assign" instead.
Second, like I said the variable was not well declared. It consisted in a 16 bit register and not a 16 position array, with 32 bit variables.

b_array [0]= 13;

In this code you try to load "13" into one "bit". Impossible. It would not work and it probably is the reason why you don't have the right results..

Write like this:

module max11_tb();
reg [0] b_array;

assign [0][31] b_array = ...whatever...
.....
assign [15][31] b_array = ...whatever...
endmodule

You must also change The code inside the "for" cycle to access to "b_array" correctly.

for (i=0;i<15;i=i+1)
begin
if (b_array[31] > mxm)
mxm = b_array[31];
end

And I think this is all.

If you want some tutorials and examples check for:
https://www.asic-world.com/verilog/veritut.html

It might be usefull.

Added after 5 minutes:

fcfusion said:

There is a lot of wrong stuff here and 1 of the errors is mine:
1)

input [0] b_array;

Click to expand...

I suggested this but I was wrong, and should be:

reg [31] b_array [0]

Click to expand...

This is the correct way and I actually sugested it right in some of my previous posts but then sugested it wrong in my last

2)"Initial" blocks are NOT synthesizable. They are used only for simulation purposes. So use the "always @(posedge clk)" like I sugested. The simulation might still work anyway but that's some really bad coding.

3)

initial begin
// Initialize Inputs
b_array [0]= 13;
b_array [1]= 1;
b_array [2]= 2;
b_array [3]=14;
b_array [4]=12;
b_array [5]=0;
b_array [6]=-1;
b_array [7]=21;
b_array [8]=12;
b_array [9]=2;
b_array [10]=-4;
b_array [11]=0;
b_array [12]=9;
b_array [13]=13;
b_array [14]=10;
b_array [15]=-2;

Click to expand...

There are two errors here. First, if you want to initialize the variables do not use "initial". Might still work in simulation though. Use "assign" instead.
Second, like I said the variable was not well declared. It consisted in a 16 bit register and not a 16 position array, with 32 bit variables.

b_array [0]= 13;

Click to expand...

In this code you try to load "13" into one "bit". Impossible. It would not work and it probably is the reason why you don't have the right results..

Write like this:

module max11_tb();
reg [0] b_array;

assign [0][31] b_array = ...whatever...
.....
assign [15][31] b_array = ...whatever...
endmodule

Click to expand...

You must also change The code inside the "for" cycle to access to "b_array" correctly.

for (i=0;i<15;i=i+1)
begin
if (b_array[31] > mxm)
mxm = b_array[31];
end

Click to expand...

And I think this is all. You should use the code I sugested earlier but correct everything regarding "b_array". I think it will work well this time.

If you want some tutorials and examples check for:
https://www.asic-world.com/verilog/veritut.html

It might be usefull.

Click to expand...

Added after 1 minutes:

You should use the code I sugested earlier but correct everything regarding "b_array". I think it will work well this time.

UFK · May 30, 2010

Re: Verilog debugging!

My dear friend
I believe ur patience has run out by now. I cant this little code straight.
The code and the tb both simulate fine now. I guess there is this one little thing missing in the tb which is why i cannot display the largest number in the array.
I made changes in my code as per ur suggestions, some worked fine, others gave me errors so i tried correcting. Here it is.

The code

module maxvalue(clk);

reg [15:0] b_array [0:15];
integer i;
reg [0:15] mxm= 16'b0;
input clk;

always@(posedge clk)
begin
for (i=0;i<15;i=i+1)
begin
if (b_array[15] > mxm)
mxm = b_array[15];

$display("The maximum value is: %b", mxm);
end
end
endmodule

And the tb. And it gave me 5 errors without the initial begin

module maxx_1_tb;

// Inputs
reg clk;
reg [31:0] b_array [0:15];
reg [0:15] mxm;

// Instantiate the Unit Under Test (UUT)
maxvalue uut (
.clk(clk)
);
initial
begin
// Initialize Inputs
clk = 0;

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here
b_array [0]= 13;
b_array [1]= 1;
b_array [2]= 2;
b_array [3]=14;
b_array [4]=12;
b_array [5]=0;
b_array [6]=-1;
b_array [7]=21;
b_array [8]=12;
b_array [9]=2;
b_array [10]=-4;
b_array [11]=0;
b_array [12]=9;
b_array [13]=13;
b_array [14]=10;
b_array [15]= -2;

end
endmodule

Click to expand...

If you run this ull see it displays everythng except what i demand from it. The maximum value!
*sigh* my advisor will kill me for not even managing this tiny code, that too with external help (you)
btw u have been very very patient and helpful. Thanks alot

Welcome to EDAboard.com

Debugging Verilog code for calculating the maximum value in an array

UFK

Member level 3

fcfusion

Full Member level 4

UFK

Member level 3

fcfusion

Full Member level 4

UFK

Member level 3

UFK

Member level 3

fcfusion

Full Member level 4

UFK

UFK

Member level 3

fcfusion

Full Member level 4

UFK

UFK

Member level 3

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Connect with us

Online statistics

Forum statistics