circuit/verilog for frequency comparision

module frequency_comparator(
    input clk_sys,
    input clk_a,
    input clk_b,
    input rst_n,
    output a_is_faster
    );

reg [2:0] rsync_clk_a;
reg [2:0] rsync_clk_b;

// Resynchronize clk_a and clk_b inputs to the main clock domain.
always @(posedge clk_sys or negedge rst_n) begin
    if (~rst_n) begin
        rsync_clk_a <= 3'b000;
        rsync_clk_b <= 3'b000;
	 end else begin
        rsync_clk_a <= {rsync_clk_a[1:0], clk_a};
        rsync_clk_b <= {rsync_clk_b[1:0], clk_b};
    end
end

// Find the rising edges of clk_a and ckl_b.
// On a rising edge, edge_detected goes high for 1 main clock period.
wire edge_detected_a = (rsync_clk_a[2]) & (~rsync_clk_a[1]);
wire edge_detected_b = (rsync_clk_b[2]) & (~rsync_clk_b[1]);

thats_no_pfd thats_no_pfd(
  .clk(clk_sys),
  .rst_n(rst_n),
  .edge_detected_a(edge_detected_a),
  .edge_detected_b(edge_detected_b),
  .a_is_faster(a_is_faster)
  );

endmodule // frequency_comparator

module thats_no_pfd(
    input clk,
    input rst_n,
    input edge_detected_a,
    input edge_detected_b,
    output reg a_is_faster
    );

reg [1:0] count;
// If a is faster, this counts up. If b is faster this counts down.
// With a 2-bit counter it takes 4 sustained counts in either
// direction before the "a_is_faster" output will change. It takes 4 times edge_detected_a
// before "a_is_faster" goes high, or 4 times edge_detected_b before "a_is_faster" goes
// low. Change counter size to adjust for preferred level of hysteresis.

wire count_max =  (& count);
wire count_min = ~(| count);

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        a_is_faster <= 1'b0;
        count <= 0;
    end else begin
      case({edge_detected_a, edge_detected_b})
        2'b00: ; // nothing happening...
        2'b11: ; // a and b both changed, so no DIFFERENCE count
        2'b10: begin // a faster
                 if (count_max)
                      a_is_faster <= 1'b1;
                 else
                      count <= count + 1; 
              end
        2'b01: begin // b faster
                 if (count_min)
                     a_is_faster <= 1'b0;
                 else
                     count <= count - 1;
               end
        default: ;
        endcase
    end
end

endmodule // thats_no_pfd

module bench_frequency_comparator;

	// Inputs
	reg clk_sys;
	reg clk_a;
	reg clk_b;
	reg rst_n;

	// Outputs
	wire a_is_faster;

   // Helper signals
	reg swap_clocks;
	wire swapped_clk_a = (swap_clocks == 1'b1) ? (clk_b) : (clk_a);
	wire swapped_clk_b = (swap_clocks == 1'b1) ? (clk_a) : (clk_b);

	// Instantiate the Unit Under Test (UUT)
	frequency_comparator uut (
		.clk_sys(clk_sys), 
		.clk_a(swapped_clk_a), 
		.clk_b(swapped_clk_b), 
		.rst_n(rst_n), 
		.a_is_faster(a_is_faster)
	);

	initial begin
		// Initialize Inputs
		clk_sys = 0;
		clk_a = 0;
		clk_b = 0;
		rst_n = 0;
		swap_clocks = 0;

		// Wait 100 ns for global reset to finish
		#100;
		rst_n = 1;
	end

        // 50 MHz main clock
        always begin
            # 10 clk_sys = !clk_sys;
        end

        // 24.390 MHz clock A
        always begin
            # 41 clk_a = !clk_a;
        end

        // 23.810 MHz clock B
        always begin
            # 42 clk_b = !clk_b;
        end

        // every 10 us swap the test clocks around to see how the output recovers
        always begin
            # 10000 swap_clocks = !swap_clocks;
        end

      
endmodule // bench_frequency_comparator