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What does VPT influence setup/hold time? Anyone can help?

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jason7361

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Hi!

I have question on how voltage, process, and temperature will affect setup and hold time violation, can anyone explain to me?

What's the worst case ? what's the best case?

Thank you.
 

Re: What does VPT influence setup/hold time? Anyone can help

setup time ( Maxtime) violations occurs when things get slower
hold time (Mintime) violations occurs when things get faster.

So How do things get slower ?
- Slower PMOS
- Slower NMOS
- Lower Voltage
- Higher Temperature or Lower Temperature (Due to Temperature Inversion)

So setup time (worst case) is run at sslh or ssll corner


similarily how do things get Faster ?
- Faster PMOS
- Faster NMOS
- Higher Voltage
- Lower Temperature
So Hold (Best case) is run at ffhl corner

also the industry standard name is PVT ( its not VPT)
 
Re: What does VPT influence setup/hold time? Anyone can help

Thank you for replying, I got it.
 

@koggestone, well said.

Thats the reason people will always characterize their libraries for various PVT corners.

Some thing like fast-fast, typical, slow-slow & etc.
 

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