Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

PMOS pass device in LDO needs to be in SATURATION always?

Status
Not open for further replies.

allennlowaton

Full Member level 5
Joined
Oct 5, 2009
Messages
247
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,298
Location
Taiwan
Activity points
3,066
hello guys...
i'm doing LDO now, I'm just wondering, do I need to operate the PMOS in saturation always during its operation? If not, why?

thank you very much...
 

No. Linear region is good for load transient in order to reduce recovery time and spike current.
 
thank you for your reply shaq..
i had read something here in edaboard.
it says

PMOS not always in Saturations. Depend on VIN, VOUT. If
- Vout<VIN-Vdsat, it will be on sat
- Vout> Vin-Vdsat, it will be on triode

...i try to confirm this..but, it seemed wrong simulation result...
..any idea about this?
 

Re: PMOS pass device in LDO needs to be in SATURATION always

It depends if you are operating in dropout region PMOS will be in linear region and If vout-vin > drop out voltage ,PMOS will be in saturation region..

Some times PMOS is always operated in linear region to save chip area at the cost of PSRR..

-rampat
 
thank you rampat...
i'm confused with the drop out voltage...
i try to find the value of drop out voltage in the .lis file of HSPICE.
is it the Vdsat or the Vds?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top