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Difference between clock buffer and normal buffer?

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Hi,

Could someone tell me the difference between clock buffer and normal buffer?

Is it true that clock buffer consumes more power than normal buffers? If so how?
 

Clock buffers are usually designed such that an input signal with 50% duty cycle produces an output with 50% duty cycle. This usually isn't true for a normal buffer.
 
Hi,

Could someone tell me the difference between clock buffer and normal buffer?

Is it true that clock buffer consumes more power than normal buffers? If so how?
Click to expand...


clock buffers have equal rise and fall times with different drive strenths, whereas the normal buffers may not have equal rise and fall times.

to make equal rise and fall time in a clk buffer we make the pmos double the size of nmos thats why it consumes more power.

correct me if I am wrong...
Click to expand...
 
for equal rise/fall time ,

1) In older processes like .13u & above , Pmos Width is 2X of Nmos
i.e Beta ratio of 2.

2) in 40nm process , it is ~1.5X

3) in 28nm process , i guess it is ~1.3X

The reason PMOS Mobility is getting better is bcoz of Strain Engineering ( basically
for PMOS , u "push" atoms so that holes can move faster) .

Similarily to improve NMOS Mobility , u "pull" atoms so that electrons can move
faster in between them. (something like u can run faster in a Less crowded
road than a more crowded Road)

(Impress your Interviewer with above concepts in your next Job Interview!!)
 
very helpful explanation of clock buffer.
 

keep 50% duty is the first task of clock buffers. sometimes foundry will insert some other deviced into clock buffers to avoid attenna effect...
 
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In addition to koggestone's great summary, clock buffers sometimes have input and output pins on higher metal layers to avoid the need for vias in the root clock distribution network. Normal buffers have pins on lower layer like metal 1. It's better to keep clock routing on upper layers (until near the leaf / FF). So you get clock buffer --> vias from M1 output pin up to top layer --> wiring to next buffer etc.

With pins on upper layer, much fewer vias are needed (they can be more efficiently implemented inside the buffer cell.) Some libraries also have clock buffers with input pins on high metal and output pin on low metal. These are used between global and locak clock distribution.
 
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good info koggestone and randyest
 

Very good information by Koggestone and Randyest, keep it up.
 

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