Unconnected output port in Design Vision

VSMVDD said:

you fail to initialize the 'reg' array or its variable's

module PC(din, dout, load, countEn, rst);
input[7:0] din;
input load, countEn, rst;
output[7:0] dout;
reg[7:0] dout;


you must initialise the reg as an 8 element array
i think the syntax is

to actual declare the structure you define
here is a simple bridge code from 8 bit bi dir 16 bit data to 16 bit word bus

you actual have to declare the register structure
or its not valid and the compiler etc will throw one


here is a valid code block from a bridge code
to allow atari acsi 8 bit overword transfer to 16bit word syncro
to further allow coms with spi

youll find the full project on jookies site here

**broken link removed**


`timescale 10ns/1ns

module main(aDATA,bDATA,ACK,DRQ,INT,CS,A1,GotCmd,Do,Done,PIOnDMA,RnW, CLK, ClrCmd);
inout [7:0] aDATA;
input ACK;
output DRQ;
output INT;
input CS;
input A1;

inout [7:0] bDATA;
input Do;
output Done;
input PIOnDMA;
input RnW;
output GotCmd;
input ClrCmd;

input CLK;

>>>>>>>>elements of reg array these are initialisers also so set inital val

reg [7:0] rDATA;

reg mDo = 0;

reg rINT = 1;
reg rDRQ = 1;
reg rDone = 0;
reg rGotCmd = 0;

reg Hold = 0;

reg prevCS, prevACK;

>>>>>>>>>>>>>
>>> ie reg has 8 elements declared before posedge detect begin cycle
>>> mDo[0] rINT[1] rDRQ[2] rDONE[3] rGotCmd[4] Hold[5] prevCS[6] prevACK[7]

= 8 elements filled logicaly 0-7 as elements or array NODE'S

then you can compare the control register like as byte or nibble
ie 4 or 8 bit control struct
as registers are control structures ie msb 00000110 lsb
as is before begin routine change of the 'control' register

//---------------------------------------
always @ (posedge CLK)
begin
if(!mDo && Do) // posedge Do
begin
if(PIOnDMA) // PIO
begin
rINT = 0; // the INT to L
rDRQ = 1; // restore the DRQ
end else // DMA
begin
rDRQ = 0; // the DRQ to L
rINT = 1; // restore the INT
end

if(RnW)
begin
rDATA <= bDATA;
end

rDone <= 0;
mDo <= Do;
end

if(mDo && !Do) // negedge Do
begin
rDone <= 0;

mDo <= Do;
end
//----------------
if(ClrCmd) // clear Done
begin
rDone <= 0;
rGotCmd <= 0;

rINT = 1; // restore the INT
rDRQ = 1; // restore the DRQ
Hold = 0;
end
//----------------
if((prevCS && CS) || (prevACK && ACK)) // if signal is H
begin
Hold = 0;
end
//----------------
if((!prevCS && CS) || (!prevACK && ACK)) // if raising edge
begin
Hold = 1;
end
//----------------
// if(!CS || !ACK) // if I should latch the data
// if(!CS || (!prevACK && !ACK)) // if I should latch the data
if((!prevCS && !CS) || (!prevACK && !ACK)) // if I should latch the data
begin

if(!RnW && !rDone) // write?
begin
rDATA <= aDATA; // from ST to AVR
end

Hold = 1;

if(!CS)
begin
rINT = 1;
end

if(!ACK)
begin
rDRQ = 1;
end

if(!CS && !A1) // if command was received
begin
rGotCmd <= 1;
end

rDone <= 1;
end
//----------------
prevCS <= CS;
prevACK <= ACK;
end
//------------------------
assign bDATA = (rDone && !RnW) ? rDATA : 8'bz;
assign aDATA = ((!CS || !ACK || Hold) && RnW) ? rDATA : 8'bz;
assign INT = rINT ? 1'bz : 0;
assign DRQ = rDRQ ? 1'bz : 0;
// assign INT = rINT;
// assign DRQ = rDRQ;
assign Done = rDone;
assign GotCmd = rGotCmd;
endmodule

Added after 26 minutes:

module PC(din, dout, load, countEn, rst);
input[7:0] din;
input load, countEn, rst;
output[7:0] dout;
reg[7:0] dout;
reg d0,d1,d2,d3,d4,d5,d6,d7;



will work with no compiler error

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Syswip said:

When are you running check design after compilation or before?

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