Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

About the Calibre LVS

Status
Not open for further replies.

gaom9

Full Member level 4
Joined
Oct 8, 2007
Messages
228
Helped
7
Reputation
14
Reaction score
5
Trophy points
1,298
Location
China
Activity points
3,294
calibre lvs user guide

Hi,
I have a question about the LVS of Calibre.
In my design, some parameters mismatch in layout can be ignored, how can I set the Calibre to pass the LVS. For example, I want to set the match percent of the MOS1 to be 90%, how can I set it in Calibre.

Thank you!
Best regards
 

lvs reduce parallel mos

Hi gaom09,

In Calibre go to Setup menu>LVS option.
Then Click "Report" Tab> LVS Report Options>More Options then select E1=Ignore missing properties used in TOLERANCE clauses of LVS REDUCE.

I hope this helps.

Cheers
 

    gaom9

    Points: 2
    Helpful Answer Positive Rating
series capacitor lvs

Hi, fixrouter4400
Thank you for your reply.
I have read the user guide of the Calibre, and found if I want to set the tolerance of the device, I should add some control word to the simulator. For example, I want to set the MOS tolerance is 5%, so I should write the control word as fallowing:

LVS REDUCE PARALLEL MOS YES [TOLERANCE L 5 W 5]

Is it right?
But I don't know where I should add this words to? Should I add to the netlist from the SCH or anywhere alse?

Thank you!
Best regard!
 

calibre lvs reduce split gates

Hi gaom09,

That's right! just follow the simple LVS Reduce instruction program and put it in the "Include SVRF Commands" option.

Please see the attached image for more info.

I hope this help you.

Cheers
 

    gaom9

    Points: 2
    Helpful Answer Positive Rating
calibre lvs problem mismatch

fixrouter4400, thank you very much.
 

caliber lvs tip

Or, if i understood your question and the mismatch is between layout and schematic. you should use the tolerance factor in TRACE PROPERTY for that specific device or set of devices.
 

lvs options in calibre

Be careful - once you enable this tolerance, it is applicable for all devices named so-n-so - or device-type even more dangerous.

If you think - you want to allow this tolerance - for few specific instances - not for all instances - I am not sure there is any way to allow instance specific tolerance.
 

lvs options allow

Hi Dude,

I got struck in LVS while running LVS, segment resistor are not recognize as a single resistor and also in LVS Setup option its showing below message

LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS NO
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS NO
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES

How to make YES in LVS REDUCE SERIES RESISTORS

find the attached LVS report file.

Plz suggest me some tips to get rid of this problem.

Regards,
Raj

fixrouter4400 said:
Hi gaom09,

That's right! just follow the simple LVS Reduce instruction program and put it in the "Include SVRF Commands" option.

Please see the attached image for more info.

I hope this help you.

Cheers
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top