Charge pump operation -- plz check

I am simulating a charge pump in C65nm. Icp is 500 uA. The schematic and resulting waveforms are attached.
The questions i have:

1. The up and down currents are not equal, the charging current reaches close to the max current (~484uA) but the discharging current only reaches (~170uA). What needs to be done to make them equal?

2. What could be done to suppress the current spikes at the transition edges?

3. The PMOS have Width of 8.4um and NMOS has width of 6um, doubling the width of PMOS increases the spikes so this is sort of an optimum for minimum spikes. Are the current waveforms and Vtune voltage correct ?

Please answer the above question, thanks in advance.

Points will be awarded to helpful answers.

haadi20 said:

I am simulating a charge pump in C65nm. Icp is 500 uA. The schematic and resulting waveforms are attached.
The questions i have:

1. The up and down currents are not equal, the charging current reaches close to the max current (~484uA) but the discharging current only reaches (~170uA). What needs to be done to make them equal?

Click to expand...

This kind of current mismatch is caused by the different properties/parameters of the NMOS and PMOS units used in the CP - and it will lead to phase errors.
Therefore, it makes sense to reduce this mismatch. Try other transistor parameters or a different and somewhat more complex CP circuitry. Some alternatives are proposed in relevant papers.

Added some minutes later:
Look for example at
www.waset.org/ijecs/v2/v2-1-3.pdf

S.A. Haadi20,

The mismatch of first order currents are from p-ch and n-ch mismatches as stated above. Also due to replica circuit bias point and output branch bias point of your circuit being different there will be mismatch due to Vds modulation effect. Suggested paper above uses active cascodes to counter Vds mismatch errors.

As for glitches your circuit has swithes at the output branch those turns on and off the current mirrors so switching glitches will couple to output. Also since current mirrors going through saturation, linear and cut off regions their Vds terminal voltages vary needing charge and dischage causing large glitches. Suggested paper above places switches differentially and than switched currents passes through one or two current mirrors those would low pass filter. Also current sources never get cut off.

looking your output signals I see that your charge pum is not stabilized yet (almost there exponantially aproaching but not there yet). Still output is charging up so p-ch naturally would provide more current. I suggest running longer simulation (or if you guess where output is heading from previous simulations you could initialize output starting from that point). If you do this initialization of output voltage by .IC you could have a stabilized output where aside circuit mismatches (n-ch p-ch mismatches and output stage to earlier stage voltage mismatch) currents would be much closer.

If you do not like to use active cascodes than there are charge pump schemes where there is a duplicate branch which tracks output branch voltage and output switch current is dumped to that branch or to output depending of the clock phase. That vay current sources aside from glitching disturbances always on and their Vds voltages more or less the same. This reduces glitches dramatically also prevents current source cutting of (going into linear region and than cutt off region) and coming back to saturation region again and vice versa. to do this switches and current mirrors need to swap places.

good luck.