How to reduce the resistance error in IC process?

Hi,
I want to know how to reduce the resistance error in IC process. As I know, the resistance is hard to make accurate. There is often a big error with it, for example, the most accurate polyresistance will have ±15％ error from the process, which contains the implantation and the error in the mask. But ±15% is too large to me, how to reduce it, and make the resistance more accurate. And one way is to use the accurate resistance out off chip, but this way do not meet me. My purpose is to reduce the error to ±5% without adding extra process, is it possible?


Thank you!
Best regards!

hi!

hopefully, it is possible to reduce the impact of the resistance variation even under 5%.
you have to use the ratio of resistance.
in fact, if the value of two resistances vary about 20% , so the ratio of these resistance will have better accuracy.

finally, try to use resistance as ratios.

hope this help.

regards.

imar said:

finally, try to use resistance as ratios.

Click to expand...

@imar: Well, you are right, the resistance ratio can have relatively low variation, but resistance ratio is not really a resistance, is it?

In general, the value of your resistor depends on its dimensions and doping concentration (among several other things). While you can increase its dimensions (and minimize the associated error), you can not influence the error in doping concentration. This error depends on your process (you said it yourself as well!!!), if you have 3σ=15% in your process that sounds as the absolute limit to me!

To conclude - you CAN NOT have a precise IC resistor.

malizevzek said:

but resistance ratio is not really a resistance, is it?

Click to expand...

absolutely right. i wanted to raise the fact that the only case that we can reduce the resistance variation is when using ratios of resistors.

and as you said WE CAN NOT have a precise IC resistor. but at least, we have to try to protect these resistances from different other process variations by having a good matching when making the Layout which is an important point that should be taken in account.

regards.

Part of the resistence error may be mitigate by having some expedient in layout design.
Poly printability is a potential source of error. To mitigate this just increase poly width in resistence design.
Poly etching is another potential source. Create a resistor matrix (3x3 or 5x5) end use the center resitor only.
Terminal resistence must to be negligible. Increase number of contacts poly to metal in order to decrease their resistence and draw them as close as possible to Silicide Block layer.
This may help to decrease the error, but as malizevzek already stated, it is difficult to have less than 5% error from nominal.
If you have chance to tune your circuitry, you may draw 2 equal resistors with a common-centroid configuration and measure 1 of them. In this way you know the other one with an error less than 1-2%.

Hope thi can help.

So I have to consider this error in design. Some error can be tolerated, but in my bias circuit, the error of resistance will cause a big problem, My bias circuit is a bandgap circuit will a resistance. And is there any bias way without resistance but have a good stable parameter?

Thank you!
Best regards!

If that resistor value is so critical for you, you can still use on-chip calibration.