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Guard rings around pmos

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dac5bits

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sharing of nwell in device and guard ring

when the PMOS source is connected to the well to remove the body effect (standard CMOS n-well process) should the guard ring surrounding the pmos be an n-well connected vdd or a substrate contact ring connected to vss?

Thanks for looking.
 

substrate contacts reduces ur substrate resistance and hence whatever noise injected by the device to subs will have low resistance path to ground.

If you have an nwell guard ring then it will isolate the device from noise from external sources reaching the device by providing isolation.

So if you want both isolation as well as prevent other circuits from the noise generated by pmos device then its better to put a substrate conn ring to gnd first then around that n-well guard ring connected to VDD.
 
fredflinstone said:
substrate contacts reduces ur substrate resistance and hence whatever noise injected by the device to subs will have low resistance path to ground.

If you have an nwell guard ring then it will isolate the device from noise from external sources reaching the device by providing isolation.

So if you want both isolation as well as prevent other circuits from the noise generated by pmos device then its better to put a substrate conn ring to gnd first then around that n-well guard ring connected to VDD.
Click to expand...

fredflintstone thank you for replying. What I have are several pmos devices next to eachother with their respective back gates connected to their sources and only the gates are common to all pmos devices.

Size is important so as a minimum precaution could I just use the nwell guard rings connected to each pmos to provide the isolation between the pmos devices sharing the common gate? or could I get away with no guard rings at all?
 

do these set of PMOSs form a current mirror? then its better to place them near to each other for better matching. Since you told that they only have gate terminal common and S and D are not shared you have to place them in different n wells. If the switching activity of the circuit is critical then you have to have subs contacts as well as n well gaurd ring around each mosfet.

I have no idea what sort of circuit you have. But if its a quiet circuit which needs isolation from other blocks then you could get away with just one nwell guard ring around the whole bunch of PMOS transistors.
 

fredflinstone said:
do these set of PMOSs form a current mirror? then its better to place them near to each other for better matching. Since you told that they only have gate terminal common and S and D are not shared you have to place them in different n wells. If the switching activity of the circuit is critical then you have to have subs contacts as well as n well gaurd ring around each mosfet.

I have no idea what sort of circuit you have. But if its a quiet circuit which needs isolation from other blocks then you could get away with just one nwell guard ring around the whole bunch of PMOS transistors.
Click to expand...

it is a source degenerated ratiod current mirror so the sources will be at slightly different potentials

(hence the earlier question about using dummy transitors when the pmos source is connected to the bulk)
 

Then I think you can use one sinle n well guard ring around the whole block. Coz u only need to worry about the substrate noise coupling from blocks external to the current mirror block. Individual pmos to pmos isolation may not be required.

btw, why do u want to short the source and backgate of these PMOSs? You could have connected all the backgates to VDD. This could help you save some die area.
 

    D

    dac5bits

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fredflinstone said:
Then I think you can use one sinle n well guard ring around the whole block. Coz u only need to worry about the substrate noise coupling from blocks external to the current mirror block. Individual pmos to pmos isolation may not be required.

btw, why do u want to short the source and backgate of these PMOSs? You could have connected all the backgates to VDD. This could help you save some die area.
Click to expand...

I'm not the designer otherwise I sure would have connected the backgates to vdd.

anyway thanks for helping.
 

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