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Hi,
I dont know how you are feeding the data in as you do not say and because we are engineers, not mind readers on this forum I cannot help you with this part.
Regarding the CD74HC164E shift register, data is clocked into this device one bit at a time moving from bit 0 (the LSB - Least significant bit) to bit 7 (the MSB - Most significant bit) with each clock pulse. (So make sure you send the data byte in in the right direction)
To drive this chip:
Set pins 9 and 2 high, then put your first data bit onto pin 1, then pulse the clock input - pin 8 high and then low, change pin 1 to the next bit in your sequence and pulse the clock pin high - low again, repeat until all 8 bits are clocked in, the output will then display the data you want. If you want to stop the data set pin 2 low but do not clock the device. If you want to switch off all the LEDs at once set pin 9 to zero.
It may be wise to use small n-channel MOSFETs like a Zetex ZVN0124A to drive the LEDs if you want them to be really bright. Feed the logic output through about a 47K resistor and include an appropriate drain resistor in series with the LED to give about 10 to 20mA through the LEDs. For 5V a 220R should be OK as this will pass about 15mA alowinf for the forward voltage drop in the LED.
I hope this helps, Regards
Bob.
It works thank you very much for your detail explanation
"feeding data" English is not my first language Thats why i couldn't explain my Problem clearly
One more Help Please
Now i want to shift the data which contains in register to another register, and fill the empty register with new data (continuously fill 5 CD74HC164E):|
Hi miyaw,
To cascade 5 CD74HC164Es together you need to join together all the clock pins (pin8), connect all the master reset pins together (pin9) and all the pin 2s together so these switch at the same time. to get your data to flow between devices join the Q7 output (pin13) to the input pin of the next device in the circuit (pin1), do this for each device up to the 5 that you want to link. Then you can control all the devices at once, remember that you will need 40 clock pulses for data to travel from the input to the last bit in you 40 bit shift register that you have now created, this can go on for up to ten devices linked together if you want to, after that you will exceed the recommended fan-out for most driver logic gates so you have to use buffer gates to make the circuit work within the manufacturers recommended parameters. I hope you understand my english OK and I have not written it in a too complicated way, please ask if you do not quite understand anything.
Bob
Hi miyaw,
I think it would work OK and I would not really describe it as a bad practice but it might not be the most efficient or cost effective way to achieve the required result. It will also require some quite clever software to make it work but that is true of any animated graphics display.
You should be able to use less devices if you multiplex them so that only one row is actually illuminated at once and you rely on the persistance of human vision like a television or VDU does to make the image appear solid.
This would only then require 16 CD74HC164E devices and a 64 bit output multiplexer to select the row to be displayed. The refresh rate would ideally have to be about 75 scans per second to eliminate flicker, I do not know if this would be possible with a normal microcontroller or PC without thinking about it further.
You might be able to do it with a lower update rate by using an interlaced scan method as was used with analogue television pictures for years. This scans the even rows and then the odd rows alternately so the update rate is halved.
Te numbers of devices involved will require some buffering of the logic control lines whichever method you finally use.
at which point I should use these buffers , as you said previously after 10 CD74HC164E?. I have to use 1024 CD74HC164E in my project. :|
Is there are way to check at which point my signals are getting weak. I think if I can find out the place which signal getting week I can put buffer at that place.am I correct
:|
Hi miyaw,
Use something like 74HC540 or 74HC240 octal buffer devices, this will increase your drive capability to up to 80 outputs for each of these devices used. All you need to do is to make sure that no more than 10 inputs are driven from each output. For example if you have 1024 of the CD74HC164 devices that have a common clock, master reset, and control input pins, you will need 48 of these devices 1024 * 3 / ( 8 * 8 ), that is working on a load factor of 8, which is common in logic design. The signals from your drive logic are fed to all 8 buffer inputs in parallel, then each one output can be connected to 10 of the shift register devices, get the idea? It will be necessary for you to buffer the inputs from your drivers in order to drive enough buffers to drive all your 74HC164 devices but I think you have got the idea now.
I am not sure if you are designing this system for commercial or pesonal use, because of the complexity of it, have you considered using a field programable gate array (FPGA) like the Atmel or Xlinx devices, these have a programmable core and enough output pins so that you could get the whole deisgn into one single device including all the buffers. The programming software for some of these devices is available from the manufacturers website for download and will take care of all the internal buffering equired. You might have to learn the hardware description language VHDL to program it though.
All of this seems complicated but if you do not use adequate buffering the output switching voltage of the overloaded device will drop in value until it is below the switching threshold of the device that it it is fed into, which will result in unreliable operation. The usual effect of inadequate buffering is that sometimes the circuit will work fine and at other times it will not, it is usually affected by ambient temperature.
The circut you propose is quite a major project, so the use of buffering logic cannot be avoided, if you had a maximum load of say 12 loads on one device you might get away without using a buffer but this is unthinkable with your design.
I hope that helps your understanding a bit more.
Best regards.
Bob.
Hi miyaw,
The 3 is there because there are 3 common control lines used by each 74HC164 chip, the CLOCK, the MASTER RESET and an the common input 'Control' line, the calculation actually multiplies 1048 devices by 3 common signal lines and divides by 64 (8 buffers per chip with a fan-out of 8 for each input), id does not divide by 3 and multiply by 64. I wrote it using the 'C' programming mathematical convention, sorry if I did not make it clear enough. I used a fan-out of 8 rather than 10 as this allows a little more noise rejection. You could divide by 80 rather than 64 if you want to save a few devices, this should be alright for your application, I tend to do things like that out of habit as I normally design very high reliablity devices that have to work unsupervised for years so greater noise margins are allowed as standard.
I hope that clarifies the meaning for you.
Bob.
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