finger division in layouting

Actually i want to know that how can i decide the no of fingers .why only i divide a 20/2 in 4 transistors 5/2 why not 5 of 4/2 or 10 of 2/2 ?????????? plz reply me thanks.......

Added after 57 seconds:

See for every condition we have some trade off. what will happen if you do more number of fingers, The source and draing cap will become more. If we increase the drain cap un-necessiarly it will make much load on output net.

So we should think about area constraint and source drain cap and fingering too.
In general we prefer to put less than 10um of the width for each transistor.

For example you have 20/2 transistor and better you can make it as 5/2 m=4 or 4/2 m=5.
If you put 10/2 you are not going to reduce more gate resistance, and if you some 1/2 m=20 or 2/2 m=10, then you are going to increase the source drain cap.

So you can decide 5/2 m=4 or 4/2 m=5, according to your layout floor plan. Guess understood. Correct me if I am wrong anywhere. Thank You.

Added after 2 minutes:

let if i want to made a transistor of 250/2 then how can i divide it in fingers , it may be 5 of 50/2 or 10 of 25/2 or any thing else .plz explain me in detail .I think there should be some calculation behind this ?what it should be plz if u have any sol plz tell me i m totally confused and not getting a fully satisfactory answer. thanks

For me, I made the MOS transistors as square as possible.

There are lot's of conditions buddy. For IO's minum size will follow 25um to 60 um width.
And for matching transistors we prefer to put square type, to match all the process gradients. For current mirrors we prefer to put in a row. Becoz those will be lot's of numer in fingers. If we try to put them in square it will occupy lot's of space.

So in general ckts, the transistor finger width will range from 4um to 10um or 12um.
Better not to put more than that.

For IO ckts (ESD), it will be range from 25um to 60um. We prefer to put larger width in IO's. Because we will be having more space to put VIA's. Inthose ckts, we generally consider current ratings, not gate resistance.

In normal ckts, currents ratings will be very less and the functionality and paracitics will try to reduce. Please correct me if I am wrong anywhere.

Now coming to your example, if you tell me the ckt which you are using I can help you to decide the finger width. Thank You.

Since i m very new in layouting so first i am trying to make a totally matched differential amp with 250/2 size and with the tail current of 12 ma and load as a current source. thanks

varma_cs012 said:

There are lot's of conditions buddy. For IO's minum size will follow 25um to 60 um width.
And for matching transistors we prefer to put square type, to match all the process gradients. For current mirrors we prefer to put in a row. Becoz those will be lot's of numer in fingers. If we try to put them in square it will occupy lot's of space.

So in general ckts, the transistor finger width will range from 4um to 10um or 12um.
Better not to put more than that.

For IO ckts (ESD), it will be range from 25um to 60um. We prefer to put larger width in IO's. Because we will be having more space to put VIA's. Inthose ckts, we generally consider current ratings, not gate resistance.

In normal ckts, currents ratings will be very less and the functionality and paracitics will try to reduce. Please correct me if I am wrong anywhere.

Now coming to your example, if you tell me the ckt which you are using I can help you to decide the finger width. Thank You.

Click to expand...

as you said,For IO ckts (ESD), it will be range from 25um to 60um. if the transister fingers is out of 25um to 60um, what will happen? that is to say,why are we choose the range from 25u to 60um ?

thx

Hi vaibhavbanga,

First ask ur designer abt the maximum poly width since the width of the poly is considered as the width of the transistor.

So plan accordingly.

Regards,
yaasi

what i think is that no. of multipiers are given by designer only...and regarding fingers;if it very very critical ckt.then we hav to consult it with designer that whether we can change it or not...and if it is not critical then we do it according to the space constraints...and according to the matching requirements...

Hey sissi,

I don't know what I am telling is correct or not !

But from my past experience, why we choose to put the ESD transistors width ranging from 25um to 60um, to get the minium current rating satisfy.

Because in ESD routing we will be seeing very big metals for large current ratings.
If we need to put VIAs for those big metals and to satisfy the minimum VIAs also we will use bigger widths. But I am not sure this is the exact reason.

Someone can comment on this plzzzzz

hi,varma_cs012

"to satisfy the minium VIAs",how to measure that?
i don't agree with you.if your comment is right, we should make the finger width beyond 60um,which may be better.

wish someone could give a great comment.

sissi

That's why I already told u I may be wrong. In your DRD itself you will find this range for the ESD transitors. Please look into the ESD rules.

And coming to vias current rating caliculation, In DRD you will be having the minimum current ratings for the each and single via.

I mean, like metal they will specify how much a single via can allow the current.
By using that you can caliculate the minum number of Via's required for particular current rating.

Regarding that ESD transitor width I will get bact to you soon. Bcoz I need to discuss with my team. Thank You.

25um to 60um is a good suggestion by Varma. The reason you don't want them too short (when touching the outside world) is that an ESD zap usually begins to break down the ends of the mosfet.
You want the center to break down too to spread the ESD power across the whole mosfet or else the ends will just burn. So by keeping some distance between the ends of each finger (by using 30um, 50um width) you help ESD resistance.

varma_cs012 said:

That's why I already told u I may be wrong. In your DRD itself you will find this range for the ESD transitors. Please look into the ESD rules.

And coming to vias current rating caliculation, In DRD you will be having the minimum current ratings for the each and single via.

I mean, like metal they will specify how much a single via can allow the current.
By using that you can caliculate the minum number of Via's required for particular current rating.

Regarding that ESD transitor width I will get bact to you soon. Bcoz I need to discuss with my team. Thank You.

Click to expand...

hi,varma_cs012
thank you very much for your reply.

For matching or reducing parasitic resistor.
and if you design LNA or VCO, the width should less than 5um (for example 0.18um process) to reduce the parasitic resistor of the gate.
but for low frequency, there is no difference.

source side must be at both ends.