Does using packages in VHDL(Xilinx) reduce gate usage?

writing packages in vhdl

Hello everyone, I have a program which takes much gates for 400K gates in spartan 3. The constraints ratio is now 103%. I used range for integers and dropped it to some 82%. But I'm in need of reducing lot more for adding some components. I have lots of redundant statements for LCD char,i2c. So If I use packages for lcd, so that I can send values whenever I need to that function by that way,could I reduce the occupation of gates?...Simply speaking, if I call that package for eg
lcd_char(lcd_data(1),rs,cs);
lcd_char(lcd_data(2),rs,cs);
likewise for about 10 times to send display 10 characters, will it consume about 10x the package size(gate)?....If I call that pakages multiple times, does that use more gates?...Please help...Also does declaring mroe arrays consume more gates?. Isn't there any other way to reduce gate consumption?. perhaps I use more if-else. Thanks in advance

vhdl and reduce function

no connection. your code is probebly not efficient enought, or your synthesiser is poor.

packages in vhdl

No Connection?.

Click to expand...

Thanks but What do you mean?...Packages help reducing gates or not in any means?. If not, then I can think of some other means of coding. Please suggest. Thanks again

reducing resource vhdl

you're not calling packages
you're just calling a function defined in a package
reducing arrays certainly reduces the usage of the gates
just try to make your code more efficient...
see how each part of your code is synthesized
and use other statements that use less space
you have to know what each statement will synthesize to before you write your code
to just have an idea how to write it more efficient from the start
that's all

usage of packages in vhdl

Hello,

lcd_char(lcd_data(1),rs,cs);
lcd_char(lcd_data(2),rs,cs);

Click to expand...

I wonder, how you convert that sequence into synthesisable HDL code. Clearly, you have to execute the two output transactions in a sequence, each of them taking several clock cycles (actually many clock cycles, cause display interface is slow compared to FPGA clock). In synthesisable code, you have neither delay statements nor clock synchronous processes in a function. This can only be done with some kind of sequencer or a state machine. If so, you may e. g. buffer all output statements in a FIFO and make the sequencer write them to the display, obeying an appropriate timing.

The other option is to use a processor core in the design and instruct it to perform the display I/O.

Apart from that, organizing functions in a package wouldn't change the resource count, as long as the code is functional equivalent.

Regards,
Frank

lcd_char(lcd_data(1),rs,cs);
lcd_char(lcd_data(2),rs,cs);

I wonder, how you convert that sequence into synthesisable HDL code.

Click to expand...

These are defined as procedures under packages. For eg.,
I define it this way


Process(clk_lcd)
begin
If rising_edge(clk_lcd) then
cnt <= cnt+1;
case cnt is
when 1 => lcd_char(lcd_init,rs,cs,flag_set); --(lcd_int = initalizing data bits)
if(flag_set = '1') then
cnt <= 2;
flag_set <= '0'; -- disable the flag
else
cnt <= 1;
endif; -- I will set the flag in function after lcd intialization.
when 2 => i:=i+1;
If (i <=7 ) THEN
lcd_char(lcd_ascii(i),rs,cs,flag_set);
elsif(i = 8 ) then
lcd_char(lcd_ascii(i),rs,cs,flag_set);
i:=0;
cnt <= 4; -- after writing last char,goto cnt4
end if;
when 3 => if(flag_set = '1' ) then --lcd char write cylce is complete
cnt <= 2;
flag_set <= '0'; --goto next char fetch,disable flag
else
cnt <= 3; ---if char write process isn't complete, loop here till
end if;
when 4 => Proceed likewise for other operations
when 5 => .....
when 6 => .....
when n => .....
when others => null
end case;
end if;
end process;

The above program is a sample of how I code for using packages for lcd. sine these functions are defined under "clk_lcd" which is at 2KHz(usu lcd clk) is the same clock for executing statements inside the function"lcd_inti" and "lcd_char". Just I sent the value of i for char disp. A flag named "flag_set" is also passed and returned to fn which is set when the lcd char write process is over so that the next databits can be placed in. I will at proper time,clear that flag for next data operation. This helps me keep my timming constant.So for this means of coding there seems no problem in timming constraints for lcd display.

Hello,

I see, that you use a sequencer in the process, this should be generally o.k. But I still don't understand the overall structure of your design, how the shown code could be used in a procedure and where it get's clk_lcd from?

Subprogram Always a Combinational Circuit
In hardware terms, a subprogram call is similar to module instantiation, except that a subprogram call becomes part of the current circuit. A module instantiation adds a level of hierarchy to the design. A synthesized subprogram is always a combinational circuit. (Use a process to create a sequential circuit.)
From Synopsis VHDL Reference Manual

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Apart from the question, how the VHDL compiler does allow this construct, there must be a way to schedule lcd accesses sequentially. To my opinion, it isn't possible in synthesisable VHDL this way, this only could work in simulation (usually with delay instructions in the procedure or function).

Regards,
Frank

how the shown code could be used in a procedure and where it get's clk_lcd from?

Click to expand...

I agree you. I'm sorry that I didn't mention clearly. That wasn't A VHDL PACKAGE. it was a VHDL MODULE. I didnt mention the package here.The function which you call inside a clock will operate only with resp to that. As you see, it's not synthesizable in VHDL in this way. Inside the process, I use clk_lcd which is considered as the source clock for all the statements which I include under rising_edge. So the function "lcd_char" and "lcd_init" are used inside this clock will operate at this frequency only...

The answer to your question is no. No if you use on of the predifined cores from the core generator then you will get better resource usage then if you wrote the code yourself.

E

nxtech said:

The answer to your question is no. No if you use on of the predifined cores from the core generator then you will get better resource usage then if you wrote the code yourself.
E

Click to expand...

I agree though.. But I always wonder why it's more efficient than ours.....Even codes generated from xilinx system generator tool for simulink under matlab seems to be more efficient in gate resources usage..

Its more efficient because they write the code with the specific logic and place and route requirements that will be used. Its as if they are hand mapping the code.

If you are familiar with assembly language coding for microcontrollers then you should understand.

We can do that ourselves but it is time consuming.

E