LC-VCO measurement problem

vco extracted view

Hi everyone,
I have a problem when I measure my VCO circuit.

I design a VCO using Bias-Tee as a part of output buffer.

When I measure it with a Spectrum Analyzer, I didn't see any output signal. But, I can see it consumes a lot of power. And when I increase the Voltage supply, the power consumption increases also.

My simulation in both Cadence and ADS are very good.
I pass LVS check in Cadence.

My design is showed in the attached picture.

vco configurations

Vgs=Vcc !!!
It will of course consume too much power and also You have charged drains of the MOS's of the main core by two times Cgd and Cgs and also Cgb...
Normally this VCO shouldn't work.
First check the negative impedance out between two drains of the main core and then connect the tank circuit that will have equivalent parallel impedance-at least- 2~3 times more ..
This configuration is very critical, try another one...

Don't trust too much to simulation results becausethe models might be wrong...
In my opinion, this configuration ( I don't know where you found it ) is absolutely nonsense...

bigboss

Thanks Bigboss for your comments

Maybe because of charging the Cgd, Cgs, the circuit consumes power!

However, I think, this configuration is a simple one and it uses the inductor instate of a current bias circuit. I found it in a lot of IEEE Journal-papers

The simulation in both well-known Tools are Good. if I don't trust them, how can I do?

I don't know how to check out the negative impedance using software. Can you show me how to do it?

Finally, If this circuit is rubbish, what should I do to make a better other one? And which are the most important factors when design a real VCO circuit.

Thank you very much.

lc-vco equivalent impedance

Let me say that BigBoss is right.

To check the neg impedance, remove the tank and inject an ac current in the core (drain of M1/2), measure the ac voltage and do the ratio V/I.

Be careful of one general issue: design is NOT ONLY trust on simulators, also if they are well proven. Design is first use a paper and a sheet, calculate solutions, then prove the math in simulation environment.

tecno and freq of this VCO?

I hope it can help.
Mazz

vco measurent

Thanks Mazz for your answer and showing me how to check negative impedance

However, I still don't understand why Bigboss told me that this circuit is nonsense!!! From my point of view, this VCO is an conventional structure and the most simple one

Actually I have two VCO designed. The second is designed with transformer feedback but I cannot simulate this circuit! And I cannot measure out anything from this VCO also but still consuming power

Ref:
1. K. C. Kwok and H. C. Luong, “ Ultra-Low-Voltage High-Performance CMOS VCOs Using Transformer Feedback” IEEE J. Solid-State Circuits, vol. 40, pp.652-660, Jun. 2005.
2.J. C. Chien, L. H. Lu, “40GHz Wide-Locking-Range Regenerative Frequency Divider and Low-Phase-Noise Balanced VCO in 0.18µm CMOS” ISSCC Dig. Of Tech. Papers, pp.544-545, Feb., 2007.

My VCO is designed in 0.18um CMOS process and the frequency is about 4-5Ghz

In fact, I am a newbie in designing VCO or things. I don't have much experience calculating or doing math with circuits. That is the reason why I trust too much on simulators. Can you show me how I can do math with them or which materials I should read?

If you have any comments on my VCO or about designing a good VCO, please let me know, I really appreciate it.

Thank both you guys very much.

Maybe you should change the direction of you Bias Tee during measurement.

The issue you are going to to is an hard one.
VCO's are critical blocks, highly non-linear, high freq.

One good book I've found is: Marc Tiebout, Low Power VCO Design in CMOS. You can find it in edaboard ()

Your particular problem:
-are you able to understand why the VCO is consuming power. how much power?
My opinion (but I can be wrong, not enough infos) is that the VCO is not running. It is a stable state.

Some general suggestion: a good buffer is a source follower, almost always used in VCOs. Post layout simulations can give VERY different results from schematic one (did you made them?)

Don't be afraid: all good VCO designers made a non-running VCO!

Mazz

Let me comment something on your VCO..
- There are 4 inductors and they can not be manufactured in practice and their differences in inductance values will push out or pull down the frequency.I mean there may be some resonance points more than 1.It's definitely unwanted state for a VCO..
-The MOS transistors work under hardly saturated mode and there is no enough headroom for signal swing..
-The drains are charged -very uncommon- with bias circuit.This will be killing configuration because in general bias circuit components are large and in accordingly the capacitances are also large..
-Mutual couplings are not wanted in a VCO because controlling these couplings is almost impossible..

Why don't you try more realistic workings and simpler configurations ??? There are lot of..

BigBoss

some comments on your notes:
the inductors in the schematic will be surely only two (both center tapped). If properly designed the possibility of a second resonace can be easily avoided.

It not so uncommon to design a hard switching (not current controlled) VCO, although it is desiderable to avoid it. In this case the advange will be to reduce the supply voltage.

Agree with charged drain.

Mutual coupling is today not so impossible to control. There are well proven electromagnetic simulators that can do it. Also there are lot of papers that use this kind of technique to reduce the parasitics in the tank to allow higher resonant freqs and larger tuning range.

I strongly agree with you that, for a beginner, a more "traditional" approach is desiderable. But sometimes companies need R&D...

Mazz

Mazz said:

BigBoss

some comments on your notes:
the inductors in the schematic will be surely only two (both center tapped). If properly designed the possibility of a second resonace can be easily avoided.

It not so uncommon to design a hard switching (not current controlled) VCO, although it is desiderable to avoid it. In this case the advange will be to reduce the supply voltage.

Agree with charged drain.

Mutual coupling is today not so impossible to control. There are well proven electromagnetic simulators that can do it. Also there are lot of papers that use this kind of technique to reduce the parasitics in the tank to allow higher resonant freqs and larger tuning range.

I strongly agree with you that, for a beginner, a more "traditional" approach is desiderable. But sometimes companies need R&D...

Mazz

Click to expand...

Ok, the operating frequency is around 4-5Ghz and coils will be very small at that frequency.If we consider that these coils are mechanical components, repeatibility of the coils will be more difficult and also mutual couplings will be more sensitive due to mechanical tolerances. I think, we're agree on that point.

(Because we have tried this kind of configuration to obtain a quadrature signal with 4 MOS devices and the result was a piece of shit... .)

In general, we don't use these active components that work in "hard saturated" mode because sometimes start-up problems occur even in simulations.To guarantee the start-up, a small amount of resistor helps us..

For skilroad..

Delete biasing circuit and lowerside coils in the circuit and put some small resistors to the ground.But before doing this, check the negative impedance of the active block by cutting resonance circuit when you look through into active portion indifferential mode.This is very important..

You may write down the result here.;;( at the frequency of interest)

To Mazz:
When I measure the circuit, I saw the current consumption as much as I got that in simulation (by multiply with VDD--> Power).

I cannot do postlayout simulation because of the lack of license (I can only run DRC and LVS). And we only have Star-RCXT license for running postsim some non-inductor circuits. I don't know whether It can use it for VCO!!!

As you thought, I only use two symmetric inductors in the circuit.

To BigBoss:

I really appreciate your help and explanations. I have never heard of it before. It is very useful for people like me.

By the way, I don't realize how important the drain is not being charged! Is it a big problem?

I checked the negative impedance and the parallel impedance as you told me. It's fine.

"Delete biasing circuit and lowerside coils in the circuit and put some small resistors to the ground" --> I don't really understand what you meant. is it that putting some small resistors between the coils and the ground and not to let the coils connect directly to the ground?

I really really appreciate your help. From both of you, BigBoss and Mazz. You, two guys make me understand more clearly about the circuits.

To dingjingfeng:

Thank for your comments. However, I tried to change the direction of the Bias Tee, but it doesn't work! Do you have any other comments or things about its?

...
I plan to design another VCO. There are some ideas I got from you guys

1. Use source follower as buffer stage
2. Consider to/not to use inductor as biasing current - "hard switching VCO configuration" and use a traditional one.
3. Calculate the negative impedance and parallel impedance (2 or 3 times larger)

Thank you very much for your help.

skilroad said:

To Mazz:
When I measure the circuit, I saw the current consumption as much as I got that in simulation (by multiply with VDD--> Power).

I cannot do postlayout simulation because of the lack of license (I can only run DRC and LVS). And we only have Star-RCXT license for running postsim some non-inductor circuits. I don't know whether It can use it for VCO!!!

Click to expand...

What's happening so? If your circuit is consuming same current in simulation and measurement, the only hypothesis is that the VCO is running. You should see it in a spectrum analizer, at least a small leakage.

For PLS you don't need any additional licenses respect to Star-RCXT. The extracted view will contail all circuit models and all RC (lumped or distributed RCc) interconnection parasitics. You absolutely need to solve this issue to go on designing VCOs - PLS are fundamental.

Mazz

I was really happy when you let me know that I can run postsim VCO circuit-containing inductors by Star-RCXT. So, I try to do it these days . However, I cannot find out anything from it but errors.

I cannot run Postsim my circuit.
....

I have other layout-version of my circuit in other technology (same size 0.18). And other people alway use this one !

There are some errors I got when I try to run postsim this circuit.
- lost a label.
- can't simulate the netlist file after extracting from GDS file.

I ended up find out this errors because I don't have the Inductor model for this circuit.

Here the procedure that I follow to run my circuit.
----

1. Extract gds file from my layout.
2. Put it in the same folder with

Herculesxt_xxx.rule
xxx_TYP_L23_050913.mapping
StarRCXT_xxx.cmd

edit the *.rule and *.cmd file by replace the _primary_ by name of gds file

run postsim
#hercules Herculesxt_xxx.rule
#StarXtract StarRCXT_xxx.cmd

After that, I got a *.spi file.
I change it to *.ps and edit it with
library name and model
VDD value
Vcontrol value ...

...
and put *.sp file to the same folder with *.lib and run Hspice.
---> I got nothing.
-------------------

For My circuit in other technology (TSMC)
They provide inductor model, but I cannot find and other file name
*.mapping
*.rule
*.cmd
----> I cannot run postsim my circuit.


For measurement.
I still don't feel good with my VCO. However, I will take your advice to my later VCO.

Thank you guys very much.
It's really great knowing you.

skilroad said:

Hi everyone,
I have a problem when I measure my VCO circuit.

I design a VCO using Bias-Tee as a part of output buffer.

When I measure it with a Spectrum Analyzer, I didn't see any output signal. But, I can see it consumes a lot of power. And when I increase the Voltage supply, the power consumption increases also.

My simulation in both Cadence and ADS are very good.
I pass LVS check in Cadence.

My design is showed in the attached picture.

Click to expand...

do you add a buffer for output matching?