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It will be not so "pretty stight forward" as yendori said. Minus 90dBc/Hz at 1kHz will be not an easy task on 2GHz. You will need a low noise PLL chip and good low noise VCO. Something like LMX2347 (integer PLL with -217dBc normalized phase detector noise) or similar may do the job, altough it is crytical due to the very high multiplication ratio (20000) in your case. Use of a fractional PLL chip, which allows the multiplication ratio to be lowered drastically, can be a better choise. National, ADI and Fujitsu are making some sigma-delta fractional chips.
Once I planned to use DDS for fine resolution and low phase noise, and then mutiply it to higher frequencies.Is it possible?
I planed use one 100Mhz crystal oscillator, and multiply to 400mHz,then drive the DDS to produce 110-125MHz, and multiply it with 16 to get the freq.
It will be not so "pretty stight forward" as yendori said. Minus 90dBc/Hz at 1kHz will be not an easy task on 2GHz. You will need a low noise PLL chip and good low noise VCO. Something like LMX2347 (integer PLL with -217dBc normalized phase detector noise) or similar may do the job, altough it is crytical due to the very high multiplication ratio (20000) in your case. Use of a fractional PLL chip, which allows the multiplication ratio to be lowered drastically, can be a better choise. National, ADI and Fujitsu are making some sigma-delta fractional chips.
Near-to-carrier PN problems are solved by Sigma-Delta PLL circuits.Because around the carrier, loop filter can not sufficiently attenuate the noise components therefore the near-to-carrier noises should be pushed out the bandwidth as much as possible
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