how to determine setup and hold time

setup and hold time definition

Hi All,

Can someone explain me how to determine setup and hold time for a DFF at transistor level using any spice simulator. What is the experimental setup for this? Any materials regarding the same would be very helpful.

Thanks in advance
Chethan

hold time, rise time

Hi Friend,
See my post :


And I hope getting other replies.

Regards,
Master_Picengineer.

definition of hold time and set up time

Pulse Waveform
General form

PULSE (V1 V2 Td Tr Tf Pw Period)

PULSE parameter
Default Value
Units

V1 - initial voltage
none
volt

V2 - peak voltage
none
volt

Td - initial delay time
0
second

Tr - rise time
Tstep
second

Tf - fall time
Tstep
second

Pw - pulse width
Tstop
second

Period - pilse period
Tstop
second

Define a pulse waveform using the format and ensure that it meets both the setup and hold time and then check if the output follows the input. Then assign the delay value to be a variable. Lets say for example the clock rises at 10ns. Sweep the delay variable from about 5ns to 12ns. Plot the graph and closest value of the the sweep variable to 10ns for which the output is right will give you the setup time.

I am not sure about hold time. But once you get the setup time, define a pulse waveform with that delay (to ensure it meets the setup time criteria). Make the width of the waveform as a variable and sweep it from very close to the clock edge to far away from the edge. That will give you a point at which the ouput is latched completely and then you should be able to get the hold time.

-Aravind

Added after 17 minutes:

Just to help a bit with explanation. This is an example

VSW 10 5 PULSE (0V 5V 5us 0.5us 0.5us 4.5us 10us)

The diagram gives the representation of the above pulse definition. The white line in the diagram represents the rising edge of the clock.

Notice how the pulse definition (delay variable) causes the signal to rise at 5us. To get setup time vary the delay to move the signal from far to very close to the rising edge of the clock. When you plot the results, the FF o/p will follow to the i/p for most values and fail beyond one point. After the point, the ff o/p will always fail. The diagram shows the delay variable being varied from 2us to about 5.9us. At and after 5.9us the FF fails. So take the earlier delay value for which the ff worked well and subtract it from 7 and you should get setup time.

For hold time do the same process by varying the width on the other side of the rising edge and get the hold time.

The accuracy of your results depends on the number of iterations that you can do. Once you find two points, one where ff works and once where it fails, you can do further iterations between those two points to get a more accurate results.

Hope this helps.

-Aravind

determine setup time hold time in spice

Got the wrong snap last time.