Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

resistor between source and gate of ESD device?

Status
Not open for further replies.

castrader

Member level 1
Joined
Jun 8, 2005
Messages
36
Helped
7
Reputation
14
Reaction score
1
Trophy points
1,288
Activity points
1,468
what is its use?
to protect the ESD device stand high current?
and what about its value?
 

castrader said:
what is its use?
to protect the ESD device stand high current?
and what about its value?

------------------------------------------
its about 1k-10k the value
 

No, it's just about hundreds ohm, less than 1K.
And usually it is N diffuse resistor.
 

I think when large current flow the ESD device, Cgd and this resistor will give a path for current, so that ESD device will be protected.
 

    castrader

    Points: 2
    Helpful Answer Positive Rating
also i have seen in some ESD I/O, use linear MOSFET instead the resistor, is it same?
 

Alan_Nesta said:
I think when large current flow the ESD device, Cgd and this resistor will give a path for current, so that ESD device will be protected.

I think the reason is when there is a large pulse, it will be coupled to the gate of the ggnmos and there will be current flow through the res between g and s , then settles up a voltage Vgs to decrease the breakdown voltage of the ggnos. So the discharge will be more effective.
 

then why 0 Ohm connect is worse than a fixed resistor?
 

sharpsheep said:
Alan_Nesta said:
I think when large current flow the ESD device, Cgd and this resistor will give a path for current, so that ESD device will be protected.

I think the reason is when there is a large pulse, it will be coupled to the gate of the ggnmos and there will be current flow through the res between g and s , then settles up a voltage Vgs to decrease the breakdown voltage of the ggnos. So the discharge will be more effective.


I agree with you, Ming-Dou Ker 's papers is a good reference
 

sharpsheep said:
Alan_Nesta said:
I think when large current flow the ESD device, Cgd and this resistor will give a path for current, so that ESD device will be protected.

I think the reason is when there is a large pulse, it will be coupled to the gate of the ggnmos and there will be current flow through the res between g and s , then settles up a voltage Vgs to decrease the breakdown voltage of the ggnos. So the discharge will be more effective.

True, or more specifically, the resistor build up a voltage drop instantaneously so that the the built-in current/discharge path, usually a diode-connected MOS or PNPN works first, and hence protects the other circuits.
 

several hundred to several K ohm

it can flow some current to protect
 

It's about hundreds ohm, and seems poly res is more used.
 

I remember 30Kohm is recommended in the book "ESD in IC".
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top