prcken
Advanced Member level 1
:?:hi , everybody ,how can I tackle the ESD detection circuit with Hspice using different technologies such as using 0.25um, 0.35um 0.5um libraries to achieve the same function. how can i decide the W/L of each MOSFET. and the Resistors related.
the circuit schematic and simulation results under normal power on and ESD stress are shown in the attachments. it was simulated by using TSMC 130nm process
the two cases are should be as follow:
1.Circuit Operation under Normal Power-on Transition
When the 3.3-V VDD_h and 1-V VDD_l have been powered on to 3.3V and 1V with a simultaneous rise time of 1ms., no trigger current will be generated from the ESD detection circuit into the trigger node (node 3 in Fig. 4-3) of the STNMOS.
2.Circuit Operation under ESD Transition
When ESD transient voltage is applied to VDD_h with VSS relatively grounded, the gate of Mp1 (node 1 in Fig. 4-3) is initially kept at a low voltage level (around 0V) due to the RC delay of R1 and C in the ESD detection circuit.The PMOS Mp1 and Mp2 can provide the substrate-triggered current larger than 60mA within 10ns when the 0-to-7V transient voltage is applied to VDD_h.:?::?:
the circuit schematic and simulation results under normal power on and ESD stress are shown in the attachments. it was simulated by using TSMC 130nm process
the two cases are should be as follow:
1.Circuit Operation under Normal Power-on Transition
When the 3.3-V VDD_h and 1-V VDD_l have been powered on to 3.3V and 1V with a simultaneous rise time of 1ms., no trigger current will be generated from the ESD detection circuit into the trigger node (node 3 in Fig. 4-3) of the STNMOS.
2.Circuit Operation under ESD Transition
When ESD transient voltage is applied to VDD_h with VSS relatively grounded, the gate of Mp1 (node 1 in Fig. 4-3) is initially kept at a low voltage level (around 0V) due to the RC delay of R1 and C in the ESD detection circuit.The PMOS Mp1 and Mp2 can provide the substrate-triggered current larger than 60mA within 10ns when the 0-to-7V transient voltage is applied to VDD_h.:?::?:
