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Measurement of PLL settling time [hlp]

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elec350

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e5052a vco measurement kv

hi
how we can measure settling time of a pll synthesizer? by spectrum analyzer?
 

Yes. as watermelon says:
See the control line voltage of VCO, when the voltage is become constant, it means that the PLL is locked. And the time when it's becoming constant is the setting time.

Ryan
 

The suggested method is ok, but suffer from inaccuracies; let me explain better. Suppose that your KVCO is 100 MHz/V and you want to know when the PLL has settled his freq whithin a range of 10 KHz. The voltage accuracy has to be 1^4/1^8<1 mV!!

One more accurate method is, with a spectrum analyzer that is able to demodulate the signal, use freq or phase demod and measure the freq error triggering properly.

I hope it can help.
Mazz
 

Mazz is correct, but you can use the o-scope even if the Kv is high. The PLL will settle exponentially so if you capture the Vin you can predict settling to any desired accuracy.
 

Another solution would be to use these fancy new real-time spectrum analyzers which are able to visualize the locking process by monitoring the VCO freq and look how it shifts in time
 

see the control voltage of vco is convinient
 

Spectrum analyser may be used if available. And I am sure if you've designed a PLL with Kvco of 100 MHz/V, the PLL works in GHz. A good digital oscilloscope will be cheaper than a GHz spectrum analyser.

And if the Kvco is lower, a digital oscilloscope will do very well.

And a good digital oscilloscope gives you accuracies of greater than 16 bits.
However, it all depends on available resources.
 

Agilent's VCO/PLL analyzer E5052A can measure transient frequency characteristic with very high accuracy. I used it to measure 20us settling time(0.5us
resolution) with +/-1kHz locked.
 

1. Use scope the capture the waveform of loop filter. You will see the overshoot during frequneyc change.

2. Use spectrum analyzer to measure. Set SPAN=0 for desired channel. The SA will switch to time domain. You can change the freqeuncy and you will able to capture the lock time of pll
 

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