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use N4 could decrease the NMOS current mirror dismatch wiht increasing supply voltage ,because the drain voltage of the bottem NMOS is clamped by the upper PMOS diode connection , when supply voltage increase ,the drain voltage of NMOS transistor also increase, but the NMOS current mirror is constant to VGS. so this vill casue mirror current dismatch with increasing supply voltage.
I think that the main advantage of N4 is to decrease the mismatch in the two current mirrors shown in the circuit. This is done by the voltage drop that N4 will takes , this drop will decrease Vds of The neighbours NMOS and PMOS transistors such that their Vds voltages become much closer to those of their corresponding mirror pairs . As the Vds of the transistors performing a mirror gets closer, we get better matching.
Yes I think it is done for matching.But doing like what is given in the figure will decrease the o/p resistance of the NMOS current mirror .(I mean that diode connected transistor N4 will have 1/gm4 as o/p resistance ).Is there a better way of doing it.Please correct me if i have said anything worng
Yes I think it is done for matching.But doing like what is given in the figure will decrease the o/p resistance of the NMOS current mirror .(I mean that diode connected transistor N4 will have 1/gm4 as o/p resistance ).Is there a better way of doing it.Please correct me if i have said anything worng
I think that this is not a problem because we shall be concerned with the low output impedance only at the final output of the current source where variation in the voltage (caused by variation of the common-mode input level) causes variation of the supplied current .But in intermediate stages , voltage will be constant and thus current will be constant too.
because of channel length modulation, in short channel device, the output current varies severely along with drain source voltage(vds). if you draw I-V graph(Vds
versus Id) you will see the Id is not a flat line vs Vds, that means you gotta have
two same vds if you want two transistors to have the same current. usually voltage
between nmos and pmos shifts toward either one. therefore either nmos current mirror or pmos current mirror experiences possibly high current mismatches.
to reduce this current mismatches, you can add a resistor there to cause a voltage
drop, which can reduce vds difference for either nmos or pmos mirror. but if the
current is too small, the required value of the resistor would be huge. another
possible way is adding a voltage shifter like N4 in your schematic.
someone mentioned adding N4 lowers output impedance of the current mirror. but
my opinion is different. if you see the impedance from pmos mirror to nmos mirror, it will be series connection of diode connected N4 and rds of the nmos, therefore the output impedance would be slightly increased by 1/gm of N4 compared to the case without N4
another way of looking at this is that the output impedance of a current mirror is
actually how much current is varied when vds is varied. i dont see why Id should
be varied much even though N4 is added compared to the case without N4.
N4 basically improves the PSRR of the opamp. Because if there is any variation in the power line due to coupling noise or external disturbance the bias voltage of P0 get disturbs and the bias current of P0 changes which effects in opamp performance. So, to make sure that the bais voltage of P0 is stable we need constant Vsg for P0 which is done by N4.
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