Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to model asynchronous clock in DC compiler?

Status
Not open for further replies.
S

shiv_emf

Advanced Member level 2
Joined
Aug 31, 2005
Messages
605
Helped
22
Reputation
44
Reaction score
6
Trophy points
1,298
Activity points
4,106
How to model asynchronous clock in DC compiler???

if suppose v hav two clocks in design .. both r originating from different sources .. wht cud be probable solution??
Shiv
 

Re: asynchronous clocks

If they are async clocks, i don't think you want to model them in DC. For timing/synthesis purpose, just define them as false paths. Then make sure that the signals that pass between the async clock domains are synch'ed properly.

http://vlsiforum.com
 

    S

    shiv_emf

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top