Set/Clear SIGNAL from two processes ?

Hello

I now that i cant write to a SIGNAL from to different processes, but i now need to set a SIGNAL from two processes how can i realize that ? (Some other technique)

Thanks alot in advance.



Best regards
René

can you please repeat a bit clearly
i didn't get anything
try to write in precise and correct english words please

Sorry for my bad english :-(

What i need is a technique to write to the same SIGNAL / SHARED VARIABLE from two diffent processes (If you try in Xilinx you get Multiple source on xxxxxx), so i need a technique that i do the same for me ?

Hope that was a better explanation.

Best regards
René

Hi,

If you drive one signal from two processes, it will always give you multiple driver problem. However you can use protected shared variable for the same.
have you tried using shared variable... if yes please let us know what did you get?

I have tryied shared variebles but a get the same error here (Multiple sources), but how do a declare a protected shared variable ?

Thanks alot in advance.
Best regards
René

for multiple signal drivers you should have a resolution function to determine the value of the signal, just read more about resolution functions in any vhdl book and you'll write your own easily

Hi,

Salma
If the signals are of "std_logic" type, then the built in resolution function is automatically used by the compiler. and I think we need not write resolution function. Here the case is different, he has to drive the same signal from two processes for which, I think, resolution function will not work. I may stand corrected please.....

TheBorg,
Please try to find out on the net how to declare protected shared variable, I have never used it actually. I found following lines from the net...
https://portal.acm.org/citation.cfm?id=622937&dl=acm&coll=&CFID=15151515&CFTOKEN=6184618
The VHDL standard currently allows concurrent access to variables shared between processes, but does not define any semantics for concurrency control. The IEEE 1076a Shared Variables Working Group has developed a form of monitors, called protected types, to provide mutually exclusive access to shared variables. This article identifies the problems that can arise from unprotected concurrent access to shared variables and reviews the idea of monitors, which forms the basis of the proposed language change. It describes protected types, gives some guidelines on using them for hardware modeling, and includes examples to illustrate their use.

well, std_logic are already automatically resolved
only std_ulogic aren't resolved
but u can always have user defined resolution functions
not necessarily the ones in the packages

maybe this paper will help u:

klabs.org/richcontent/software_content/vhdl/force_errors.pdf