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robust Current mirror design

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evilguy

evilguy

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cascode current mirror vgs resistor

How to design process insensitive current mirror? is it possible to design one without have to use dual Vth process to compensate process variation. i've read some paper on using dual vth process to achieve that.
 

current mirror design

As far as I know, even simple current mirrors are process insensitive, aren't they? A.
 

Almost all of the current referencing circuit is only voltage and temperature independent, like bandgap current reference. However, it's so called temperature independent only in first order approximation and you need curvature compensation. Simple current mirror is NOT process insensitive, Different process corners will cause change in Vt which affects final current output, also most of the current mirror is resistive degenerated that resistor changes as well
 

Simple current mirror is NOT process insensitive, Different process corners will cause change in Vt which affects final current output, also most of the current mirror is resistive degenerated that resistor changes as well
Click to expand...

Not True

The only problem is not Vth variation but Vth mismatch. Current mirrors are insensitive to the value of Vth.

Besides, most MOS mirrors are NOT degenerated ( except when its noise is an issue as in VCOs )

The effect of Vth mismatch can be decreased by making Vgs larger.
 

yes i agree if you said when we make Vgs large, Vt mismatch can be reduced. however if we design the current mirror for smaller process, it is difficult to make Vgs large. it is worse when we design for subthreshold region. it is posible to design current mirror in subtrehold region? what are the challenges?

i think what hung_wai_ming@hotmail.com said is also correct. drain current depends on threshold voltage. at every corner, the threshold voltage will be different. it must have some impact to current mirror that we've designed. if there are any ways to make it insensetive to threshold voltage variation, i'll be really glad to know.
 
Hi Evilguy

Thanks for your clarification.
What i emphasize here is a REAL case situation, not theory from books as from books, we always ignote 2nd order effect, so we can theoretically get a fixed output current. In reality, it is not as current always changes by say 5-10% across process for SIMPLe current mirror. Here i would say SIMPLE current mirror as if the current mirror is not simple enough, we can get better results. For example, if you use cascoded with bandgap generated mirror, it is not simple already and we can get better results.

I also really glad to know if anyone can have simple enough but process insensitive current mirror. What we can usually do is voltage and temperature independent, instead of process. Just one thing, even you place two transistors, the oxide and implant difference has already caused current mismatch that you cannot aviod by simple skills
 

i only find process insensitive voltage reference. This is the paper. using the same approach as this paper, can we design current mirror that insensitive to process?
 

Hi,

I like to know more about real design of Bandgap reference & also unable to download the paper. Please help me.

thanks
 

Blackuni said:
Hi,

I like to know more about real design of Bandgap reference & also unable to download the paper. Please help me.

thanks
Click to expand...

Use the free mirror. it dont requires point
 

evilguy said:
yes i agree if you said when we make Vgs large, Vt mismatch can be reduced. however if we design the current mirror for smaller process, it is difficult to make Vgs large. it is worse when we design for subthreshold region. it is posible to design current mirror in subtrehold region? what are the challenges?

i think what hung_wai_ming(at)hotmail.com said is also correct. drain current depends on threshold voltage. at every corner, the threshold voltage will be different. it must have some impact to current mirror that we've designed. if there are any ways to make it insensetive to threshold voltage variation, i'll be really glad to know.
Click to expand...
hi
actually,current mirror is vth variation insensitive and vth mismatch sensitive,what you said is current SOURCE,it is vth variation sensitive
 

leohart said:
evilguy said:
yes i agree if you said when we make Vgs large, Vt mismatch can be reduced. however if we design the current mirror for smaller process, it is difficult to make Vgs large. it is worse when we design for subthreshold region. it is posible to design current mirror in subtrehold region? what are the challenges?

i think what hung_wai_ming(at)hotmail.com said is also correct. drain current depends on threshold voltage. at every corner, the threshold voltage will be different. it must have some impact to current mirror that we've designed. if there are any ways to make it insensetive to threshold voltage variation, i'll be really glad to know.
Click to expand...
hi
actually,current mirror is vth variation insensitive and vth mismatch sensitive,what you said is current SOURCE,it is vth variation sensitive
Click to expand...

can you clarify it further. thanks.
 

current source is a cell which generate a fixed current,so it is vth variation sensitive as you have said "drain current depends on threshold voltage"

current mirror is a cell which make replica of current source's fixed output current.As the source is fixed,the mirror is only sensitive to vth mismatch
 

leohart said:
current source is a cell which generate a fixed current,so it is vth variation sensitive as you have said "drain current depends on threshold voltage"

current mirror is a cell which make replica of current source's fixed output current.As the source is fixed,the mirror is only sensitive to vth mismatch
Click to expand...

I agree with that. in order to mirror current, one have to design current source. So, if the source itself is deviate, then the mirror also will be varied. although the current mirror perfectly mirror the current, yet it is still not the desired current. but i think i undertand what you want to say.

let consider simple current mirror consist of M1 and M2. let assume the variation of Vth for M1 and M2 is similar, neglecting channel length modulation, both transistors' drain current is equal. On the other hand if Vth mismatch occur, means that both transistor Vth is differ by α value. then M1 and M2 will have different drain's current. in other word, M2 failed to mirror M1 current. hope this clear the explanation a bit

theoretically it is correct. Hopefully someone can clarify it in term of practical implementation.
 

ahmad_abdulghany said:
You should first think in designing a robust current source otherwise you'll assume ideal current source that you don't have actually!!
Click to expand...
yes maybe i should change the topic to "robust current source design" (how to change topic title?) and i agree that it is impossible to achieve ideal current source. i'm investigating the technique to design robust current source that work in every process corner with little variation in output current. As far as i manage to get is robust voltage reference. the technique is as i posted above.

anyone who has a lot of experience in design analog circuit, i really would like to know what is the percentage of variation that we can consider it as desirable. for example, if we design current source which the output current is 5µA. When we do PVT anaysis, the variation is about 10% from typical value. is this still consider good design or it is depend on circuit application whether the 10% variation is acceptable or not.
 

cascode current mirror is robust current mirror
this u can find following book

vlsi design techniques for analog and digital circuits by geiger
 

does anyone know about the regulated bias?
 

ya I aggre with evilguy, if i'am not mistaken there is not perfect current mirror (ideal). there is slightly +- different if we change the PVT. However, what is the acceptable +- percentage for this variations.
 

I also met some problems in robust current mirror.
I use the feedback circuit but in the high frequency it also very fragile
 

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