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Integrating ADC (duel slope)

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eecs4ever

eecs4ever

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integrating adc

Hi,

I'm interested in learning about the Integrating ADC, can someone recommend some sources?

any IEEE publications that may be useful?

Whats the typical sampling rate and number of bits for this type of ADC?

Thanks!
 

designing an integrating adc

U can easily find it out in following book:

OP-AMP & Linear Integrated ckts ----- Couhlin & Driscoll
Linear Electronics--------Gaikward
 

    eecs4ever

    eecs4ever

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dual slope integrating adc

integrating ADC(dual slope)....
source: Baker, Li's book...i think it's called CMOS design, analysis and layout
integrating ADC is usually used for resolution 16bits and above. It is a very slow device when comparing to other types of ADC..yet it is extremely accurate...

sampling rate...it takes 2^(N+1) clock cycles to finish one conversion. It takes 2^N clock cycles to charge the capacitor and it takes at most 2^N clock cycles to discharge. Thus, 2^(N+1) clock cycles.

hope that helps
 

    eecs4ever

    eecs4ever

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