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What is ECO in ASIC Design Methodology?

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eco asic

Engineering Change Order.......

basically when you mess-up and do a fix to sort it out :)
 

asic design methodology

Ex:
When you finish you desing at its ready to tapeout.. then you find that instead of and gate you add or gate in your design.. then you can't do from start.. its waste of time.. so you do eco.. such that it replaces the and gate with or gate and slightly aligns os that your precious time is not wastage mean while timing is not afftected...

similarly for nets.. if connected to some other node want to replace that..

there are many ways to doing ECO ECO by desing., ECo by netlist., ECO by area... i ECO by netlist. you generated the final netlsit and you manually add the or gate and remove and and gate then you do ECO compare netlist which will clear the violation


Regards
Shankar
 
eco fix asic

cant these errors come up when one do LVS???????????

is LVS around on same lines as that of ECO?????

thanks,
Prasad
 

rtl design eco

ECO is a procedure of fixing some timing issue after

primary layout.

best regards




Ahmed Mukhtar said:
What is ECO Please Explaine?
Click to expand...
 
asic netlist eco

ECO is Engineering Change Order as someone has already mentioned.

What it actually means is.... if we notice any issue in the design , very late in the design phase (that is after synthesis is done, 1 round of place and route is done)... then instead of going back and fixing it in the RTL (HDL) the fix is done directly in the netlist or in the layout.

This may be because of the functional bugs or timing issues.... etc

Best Regards,
Harish
https://hdlplanet.tripod.com
https://groups.yahoo.com/group/hdlplanet
 

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