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All about Timing (STA)? Primetime

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manivannanrm

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sta primetime

After reporting time. Slack and skew are the two things to check?
For skew it is 200ps is target to acheive (I am not sure) But
For slack whats tolerable value ? How to decide the slack value is tolerable ?
Setup time violation leads to " decrease in frequency " what abt hold time violation( leads to what problem?)
Thanks In advance

(If question is not clear please say it yar)
 

negative slack sta

u didnt specify your clock freq. i think your skew is ok.As far as slack is concerned, it is desirable to have a small positive slack but try to avoid negative slack.

in case of hold violation, the hold time depends on the fastest path( the path which takes least time to propagate in your logic). so if there is an hold violation means , your signal cannot propagate even the least time path of your logic. this will make your design unfit for use.it directly affects the reliablity of the chip.

if u have any more query in timing issue , kindly read the primetime user guide fundamentals and primetime modelling userguide which i have attached below .

regards
navien
 
sta primtetime

Thanks Nav_vlsi......
Its helpfull for me...............

Added after 8 minutes:

My clk frequency is 250Mhz .... how does the skew depends on clk frequency?
Does setup time ,holdtime and slack affects the fuctionality? ( is that affects only frequecy and reliability).
U have mentioned -ve slack should not be there as it is going to affect setuptime.why we r not bothered abt +slack value much.

Added after 17 minutes:

ALSO CAN ANYBODY SAW WHAT IS THE OUTPUT FILE FORMAT OF PT ?
 

hold time sta

we r not worried about positive slack as if the data comes earlier than expected wont create a problem... but if data comes late than expected can create many problems....


thanks.
Prasad
 

S but if data comes very early (hold time violations).what will be the effect on fuctionality and reliablility?
 

if data comes very early , before clock. this means ur data becomes stable before the arrival of clock pulse, thus there wont be any setup violations.also this is give rise to positive slack margin. a very high positive slack margin is a direct implication that your can still increase your clock freq. its a better practise to have a positive slack of about 1000 ps in design.
 

nav_vlsi , thats a very good explanation ...

thanks,
Prasad
 

Set up time violation leads to frequency reduction?
 

nav_vlsi said:
u didnt specify your clock freq. i think your skew is ok.As far as slack is concerned, it is desirable to have a small positive slack but try to avoid negative slack.

in case of hold violation, the hold time depends on the fastest path( the path which takes least time to propagate in your logic). so if there is an hold violation means , your signal cannot propagate even the least time path of your logic. this will make your design unfit for use.it directly affects the reliablity of the chip.

if u have any more query in timing issue , kindly read the primetime user guide fundamentals and primetime modelling userguide which i have attached below .

regards
navien
Click to expand...


Is this from SOLD?
 

if data comes very early , before clock. this means ur data becomes stable before the arrival of clock pulse, thus there wont be any setup violations.also this is give rise to positive slack margin. a very high positive slack margin is a direct implication that your can still increase your clock freq. its a better practise to have a positive slack of about 1000 ps in design.
Click to expand...

Dear nav_vlsi ,
you mention 1000ps as positive clock , do u still beleive with such high frequency chips, is it really managable??
 

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