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Verification by Non-HDL(C++/Java)??

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davyzhu

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Hi all,

I found that some verification procedure using Non-HDL such as C++/Java.

But how these Non-HDL language generate edge stimulus? Can Non-HDL also generate @posedage???

Is there any basic idea behind it?

Best regards,
Davy
 

davyzhu said:
Hi all,

I found that some verification procedure using Non-HDL such as C++/Java.

But how these Non-HDL language generate edge stimulus? Can Non-HDL also generate @posedage???

Is there any basic idea behind it?

Best regards,
Davy
Click to expand...
Hi Davy,
Take a look at TEAL http://teal.sf.net for one such approach. I would however recommend you to look at SystemVerilog instead.

Regards
Ajeetha, CVC
www.noveldv.com
 

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    davyzhu

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Hi Ajeetha,

Thank you :)

I have take a look at TEAL and wish to gain some idea.

Does SystemVerilog use some techniques other than PLI?

Best regards,
Davy
 

when two language cosimulation, the communication is through systemcall,and VPI,
delay or posedge can be implemnet in both simulator
 

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    davyzhu

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You need to check things like SystemC, E, and Vera ..
You can also try tools like ModelSim or CCSS to verify an HDL block using SystemC for example ..
 

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