Verilog Problem - All suggestions welcome

Hi - I get the following errors listed below If the commented out lines in module 2 are enabled the errors go away but then the logic is not what I require any suggestions would be welcome

error:
Warning: Latch IO_Select:IO_Select_1|CS_1_Page_1 has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal IO_Select:IO_Select_1|BankReg[0]
Warning: Latch IO_Select:IO_Select_1|CS_0_Page_1 has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal IO_Select:IO_Select_1|BankReg[0]

//////module1
always@(Write or Command)
begin
if(Command && Write)
begin
Cmd_Reg[3:0] <= PC_Dat[7:4];
Bnk_Reg[3:0] <= PC_Dat[3:0];
end
end

//////module 2 - Bnk_Reg[3:0] is connected between module 1 and 2

// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input [3:0] Bnk_Reg;
input Read;
input Write;
output CS_0;
output CS_1;
output CS_0_Page_1;
output CS_1_Page_1;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
reg [3:0] BankReg;
reg CS_0;
reg CS_1;
reg CS_0_Page_1;
reg CS_1_Page_1;
//
parameter Ext0_Ram = 4'b0001,Ext1_Ram = 4'b0010,Prog_Ram = 4'b0011;
parameter Data_Ram = 4'b0100;
//
always @(posedge Write)
begin
BankReg[3:0] = Bnk_Reg[3:0];
end
always @(BankReg[3:0])
begin
case(BankReg[3:0])
Ext0_Ram:
begin
CS_0 = 1'b0;
CS_1 = 1'b1;
CS_0_Page_1 = 1'b0;
//CS_1_Page_1 <= 1'b0;
end
Ext1_Ram:
begin
CS_0 = 1'b0;
CS_1 = 1'b1;
CS_0_Page_1 = 1'b1;
//CS_1_Page_1 <= 1'b1;
end
Prog_Ram:
begin
CS_0 = 1'b1;
CS_1 = 1'b0;
CS_1_Page_1 = 1'b0;
//CS_0_Page_1 <= 1'b1;
end
Data_Ram:
begin
CS_0 = 1'b1;
CS_1 = 1'b0;
CS_1_Page_1 = 1'b1;
//CS_0_Page_1 <= 1'b1;
end
default:
begin
CS_0 = 1'b1;
CS_1 = 1'b1;
end
endcase

end

All it is saying is this there are conditions under which the signals 'CS_1_Page_1' and 'CS_0_Page_1' which have to stay in thier previous states . The places where they are expected to remain unchanged you have written and then commented it out . So the synthesis tool was left with no other option but to infer a latch for this . This is what the warning about . Declare these signal values for all conditions of BankReg[3:0] and this error will go off . Happy coding . If you need more help do write back

Thanks for your reply. I commented them out because I want them to stay in their current state. Are you saying that the 'unsafe' warning is ok? I notice that in simulation one of the 2 lines oscillated for no aparent reason?? so I thought that the message should be taken more seriously. It oscilates even though there is no other signal changing at the time? As you can see I am new at this game, spent the last 15 years programming microcontollers and now venturing into FPGA's with great difficulty

Are the warnings ok ??? --Yes and No . It's your call YOU ARE THE DESIGNER. What you have implemented is a latch , so there is bound to be problems like the one you just said. It is usally a far better idea to use flipflops rather than latch. You can use the clock to set such problems right unless ofcourse you think that latch is what you want.

thanks for the help. but what do I do if I want two clocks? I want to clock data into the flipflop on a Read signal and on a Write signal. But if I do Always@(posedge Read or posedge Write) I get an error. This would be very easy and legal to do in hardware, I could just or the signals and feed them into the clock. I have ored them in an assign statement but cant help wondering if there is a better way to do this

davidgrm said:

I notice that in simulation one of the 2 lines oscillated for no aparent reason?? so I thought that the message should be taken more seriously. It oscilates even though there is no other signal changing at the time?

Click to expand...

That's a bad sign. That's the sign of negative feedback in a ** combinatorial ** circuit. There is no register to nullify the negative feedback.

In a real circuit, (combinatorial) negative feedback can turn a digital circuit into a big heat producing analog amplifier.

You cannot have 2 signals as a clock for your flipflop that's why Always@(posedge Read or posedge Write) does not make any sense and hence the error. What I was suggesting is something like this.
always@ (posedge Read) temp_rd = ....;
always@ (posedge Write) temp_wr = ...;
and use temp_rd and temp_wr where ever you want , I don't have your full design so I cannot for sure state wether this would work but I would say try this , if this doesn't work then try something else in the same lines.