Help me synthesize my VHDL code

Hi All,

Could anyone explain why the following does not synthesize?

I'd like to count how many times an input signal has changed.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is
Port ( a : in STD_LOGIC );
end test;

architecture test of test is

begin
process(a)
variable counter : integer := 0;
begin
if (a'event) then
counter := counter + 1;
end if;
end process;
end test;


I get the following error:
ERROR:Xst:797 - ".../test.vhd" line...: unsupported Clock statement.

Best regards.

xst: 797

Compiler is complaining because you don't have a clock signal.

in your entity add a clock input

PORT(a, clk : in STD_LOGIC);

in your architecture try this
process (a, clk);

if (clk'EVENT and clk = '1') then
if (a = '1') then
counter:= counter +1;

this is one way to do it, there are many more though.

the main thing is that you have an event but you have no conditions with the event.

another problem I see is that you named both the entity and architecture -test
I recommend changing entity to testckt or test_counter or something else.

I'm curious though as to why you have no outputs though? :?
You have it counting but with no output you can't see the results.

Hope this helps
wa

xst:797

1. You have already specified your input, a, in your sensitivity list, therefore you don't even need a'event.

2. I presume you are working on a transition counter on input, a, using an asynchronous circuit. In this case, clock is not needed. Clock is needed when you want to design a synchronous circuit.

3. use ieee.std_logic_unsigned.all; is a redundant include statement. remove it.

4. it is a bad practice to use "test of test". if you want, use "test_rtl of test", or "behavour of test".

5. you cannot synthesize a pre-assignment "variable counter: integer:=0;" and worst if you assign it in process. your code works in simulation, but will fail in synthesis. think again, how do you expect a hardware to have default value in the wires? when you design digital circuit with HDL, you have think hardware.

You can declare variable counter: integer after architecture but before begin.
Then you assign counter := 0; after begin but before process.
In this way, you have explicitly assign it outside the process. Synthesis tool will look at this as a default value stored in a LUT or SRAM.

You have a long way to go before you master VHDL.

error xst 797

Thanks people.

This is the first time I do something with VHDL. Indeed, I need to design a transition counter on input.

BTW, could you advise any good book on VHDL to get upto speed soon?

Best regards.

error:xst:797

For beginner, I recommend
"VHDL Analysis and Modeling of Digital Systems", Navabi Zainalabedin

Unlike other books (which I consider them as junks that are OK for simulation but fail to synthesize), this book gives you good foundation, teach no bullshits, good examples and teaching the right things from the beginning, and takes you further to advanced level beyond your degree.

One day, if you want to become a pro in VHDL, these are 2 good books that I seriously recommend:
1. "Designer's Guide to VHDL", Peter J. Ashenden
2. "VHDL for Designers", Lennart Lindh, Stefan Sjoholm

For the time-being, they are seriously too deep for you to learn.

The secret to do good VHDL programming for modelling, simulation and synthesis is to first be able to fully understand the circuit and system fundamantals in digital.
How can one design a hardware when he doesn't even understand how it works?

walkaround signal emule

By chance, do you have these books in electronic form?

Regards.

synthesize counter integer in vhdl

I used to download ebooks using a P2P program called emule. I have stopped using it because I prefer getting myself a printed copy from the bookstores. Nonetheless you can try searching for them. If you are bold to read deeper books, perhaps you could start exploring yourself in Ashenden's or Sjoholm's book.

vhdl assign counter

when you use a tool to synthesize your design, you must kown what pattern can be recognized by it first.
focus more attention on the code pattern pls.

error xst:797

You might try this topic.

I have this book in hard copy myself and I found it very good for beginners.



Hope this helps
wa

vhdl programming with advanced level

i think u need understand how counter operates?
It often comose some FF so it need clk to transmit count signal to output.