-ve setup and +ve hold time

Negative setup time and postive hold time?

I came across a differential FF ( had data /datab and out/outb)which has a -ve setup time and +ve hold time. This has me throughly confused. Supposed the setup time is -10ps and hod time is 30ps ,and clock starts at 0s-does this mean in the time from the 0 to 30ps if there is a transition on the data , the FF fails?.. How would you distingusih between setup violation and a hold violation?

Moreover if the data transistion is from 0 to 1 or 1 to 0 how would this affect the setup/hold time?

Would appreciate if anyone throws light on this....?

Setup time and hold time take the clock transition as reference.
tsetup is the setup time specified BEFORE the clock changes.
thold is the hold time specified AFTER the clock changes.
Usually hold time is very short specified for a standard component provided by the vendor, which may be Artisan Logic Inc for example.
To avoid setup time violation,
1. Your input signal to the component should not change during setup time.
To achieve this, all your data processing should be completed within the given time, tprocessing = tperiod - tsetup - thold, in a given cycle defined by tperiod, period of the cycle.
Many designs usually do not violate hold time, but it does happen when your input signal changes during thold. Your input signal should remain constant during thold. Hold time is violated when
1. There is transparency in input signal to the output, usually the case of a latch, but not a FF.
2. There is a clock skew, resulting the proceeding FF to clock later than the preceeding FF, AND your intermediate logic (between the proceeding and preceeding FF) processed too quickly. The resulting output (input to the proceeding FF) changes after the clock at the proceeding FF and it happens during hold time.

Setup time violation is more common. The main cause of setup time violation is due to the the intermediate logic took longer time than required to process and extended into setup time of the next cycle. To avoid setup time violation, simply try to improve your intermediate logic so that it processes faster, as long as it stays equal or less than the required processing time.

One way is to set very strict timing constraints so that your logic synthesis tool will optimise your design to the best possible timing performance.

Hi,

This is interesting. I have not notice this before, but have some thought about it.

First, what you say is correct. During simulaiton, the data signal cannot change 30ps after active clock edge, which mean that the -10ps setup is useless.

Now, is the -ve setup and +ve hold happen in the same corner? If they happen in different corners than there is no issue.

Assume they appear in the same corner, than this might be the way the FF is characterised. The way to characterise the FF is different for setup and hold. So this conflicting result might be due to characteristics.

If this case happen in the setup, then I think it is better to change the -ve setup to 0. If not, the STA will not catch this, and result in passing STA but failing simulation (and failing chip???!!!). If this is the best case corner, then I think it is fine.

Regards,
Eng Han
www.eda-utilities

Eng Han,

This FF has the -ve setup and + hold in the same corner. I cannot change the design but am trying to study the FF. My main question is how do I know if I have violated the setup time or the hold time?.. I can understand if it has +ve setup and + hold time but not in this case? So does this mean I can have only one violation with this flilflop?

Added after 2 minutes:

Sky High,

If I have a +ve setp and +ve hold time what you seem to say I can understand. but what if it is not- As in the case of this FF. It has been said to have -ve setup and +hold time in all corners?

If you cannot change the design, then do this
1. Set a very strict parameter on the clock skew, typically 0.1ns on your CAD tool so that it synthesize your design with a clock tree with the skew below or equal to 0.1ns. 0.1ns is the maximum clock skew allowed in the industry today.
I ever encountered setup and hold time violation together, and setting stricter skew limit most of the time solves my problem, in the past.
2. If this doesn't work, you might have to do re-timing, but this will involve your making changes to the design, which you must do so, else no tools can help you.

Note: I assume you are doing some RTL design with VHDL or Verilog.

If you manually route digital circuits, then you have to ask God for help. It is very complicated if you route a big and complex circuit.

Hi SkyHigh,

You miss the main issue with the FF. Let me explain.

When doing STA for setup, the STA will only use the setup value of the FF. As the FF has -ve value, it is okay for the data to arrive after the active clock edge.

However, during simulation (and if the characterisation is correct, the actual performance of the chip), the FF will have hold violation if the data change within -10ps of the active clock (i.e not setup). This is very bad as STA says okay, but infact it is not okay.

I think there are 3 solutions:
1. change the -ve setup of the FF to 0. You don't have to change the design, just change the .lib. As this changes tighten the timing, it is okay.
2. Run hold analysis in wc corner. It will catch the timing issue. However, most implementation are not run in this mode. So any issue detect here has to be correct manually.
3. Remove 10ps setup budget for all instances of this FF, or perhaps just define a clock uncertainty of 10ps (usually we try to overy-achieve setup by some margin).


Regards,
Eng Han
www.eda-utilities.com

Leeenghan and Sky high,

I am not doing a VHDL/Verilog design. I am just analysing the digital circuit for setup and hold time using Hspice. My confusion started when I had to setup a test bench for the circuit and find out the setup and hold time for it. I am not dealing with either clock skew or clock tree. I shouls say that I am very new to digital design and have heard the term setup and hold time about a handful of times without having to deal with them before.so pardon me if I ask the same thing again.


As far as I know I give a clock and a data into the FF and try to sweep the data( 0 to 1 transition) towards the +ve clock edge until it latches on the 1. If it doesnt latch to 1 but 0 then I consider the FF as failing.
In my case I cant seem to tell if they failed becoz of setup or hold violation?

There is something Enghan mentioned. If the data changes after the hold time, no violation is detected. True, but
1. If it changes due to the logic of a new cycle, it is OK.
2.If it changes due to logic of the previous cycle, then you will end up delaying the output by 1 cycle.

Using PSpice is OK. When I was an undergraduate, I ever used some "forgotten" PSpice tool to play a 4-bit D-FF and watches the transience and examine setup/hold time and even glitches. In fact, you learn better because you get to understand that digital circuits are in fact analog in nature, just the defined levels and threshold made them digital.

Don't worry. You made your test bench, and I presume you know your test vectors too.
Draw a simple timing diagram of the inputs of all FFs, clock and outputs of all FFs.
It is very easy.
Then mark the 1s and 0s on timing diagram.
Then run your simulation of the given circuit for your analysis.
Compare your drawn timing diagram and the one simulated.
You will know where the circuit has gone wrong.
The thing about cascaded FFs is that the logic is passed onto the next FF like what I would think as a ripple or a pipeline.
Then you will notice the somewhat a "staircase" or "a flight of descending steps" starting from the first FF to the last FF.

From there, you some GUI marker which you can click to make somewhat vertical red, yellow or blue line to set the "visual" margins of setup and hold time.
Visually examine the time plots of your analysis.
From there, by inspection, locate which FF and at which time there are Setup or Hold time violation.

Hi,
Can anyone tell me what the -ve or +ve stand for? "ve" is acronym of what?

If you defined the setup time to be 50ps before clock, then -ve setup time violation of 30ps is 20ps before clock.
If you defined the hold time to be 20ps after clock, then +ve hold time violation of 10ps is 10ps after clock.

Hi
I m confused about this
if I had a negative setup time of 10ps n positive hold time of 30ps n if my clk has transition at 0ps then
my data shud not change in between 10ps and 30ps !!! am i right????
please clarify it!!!!!
thanks
pra

Negative setup time and postive hold time?

The setup/hold time requirement is for data valid time, not the data transition. So the data must be stable within the clk's setup and hold time requirement.

if I had a negative setup time of 10ps n positive hold time of 30ps n if my clk has transition at 0ps then
my data shud not change in between 10ps and 30ps !!! am i right????

Click to expand...

Yes. Your signal either experiences a bad clock skew that causes hold time violation or your logic might be taking much time that causes setup time violation, thus the logic requires re-timing or modification to make it finishes faster before it enters setup time of a new cycle.

SkyHigh said:

if I had a negative setup time of 10ps n positive hold time of 30ps n if my clk has transition at 0ps then
my data shud not change in between 10ps and 30ps !!! am i right????

Click to expand...

Yes. Your signal either experiences a bad clock skew that causes hold time violation or your logic might be taking much time that causes setup time violation, thus the logic requires re-timing or modification to make it finishes faster before it enters setup time of a new cycle.

Click to expand...

Thanks for the explanation... I think I am not clear in asking the question correctly

If my data changes before 10ps does it will cause problem or it works fine!!!!

-Pra

As long as the signal changes before setup time of a new cycle, it is absolutely fine. Not to mention 10ps, even 1ps, it is fine. No setup and hold time violation at all.