I need a code to interface with VGA

module vga (clk50, VGA_Red, VGA_Green, VGA_Blue, VGA_HSYNCH_N, VGA_VSYNCH_N);
  parameter             cbits = 8;
  input                 clk50;
  reg       [cbits-1:0] count=0;
  reg            [32:0] lfsr=0;
  reg            [10:0] hcount=0;
  reg                   hlast=0, hgate=1, hsync=0, htype=0;
  output reg            VGA_HSYNCH_N=0;
  reg             [9:0] vcount=0;
  reg                   vgate=1, vsync=0, vtype=0;
  output reg            VGA_VSYNCH_N=0;
  output reg            VGA_Red=0, VGA_Green=0, VGA_Blue=0;

  always @ (posedge clk50) begin        // VGA 800x600 72 Hz
    lfsr  <= {lfsr,lfsr[32]^~lfsr[19],lfsr[31]^~lfsr[18],lfsr[30]^~lfsr[17]};
    hlast  <= (hcount == 1040-2);
    hcount <= hlast ? 0 : hcount + 1;
    hgate  <= hlast ? 1 : (hcount == 800-1) ? 0 : hgate;
    htype  <= (hcount == 400-1) ? 1 : (hcount == 800-1) ? 0 : htype;
    hsync  <= (hcount == 856-1) ? 1 : (hcount == 856+120-1) ? 0 : hsync;
    VGA_HSYNCH_N <= hsync;
    vcount <= ~hlast ? vcount : (vcount == 666-1) ? 0 : vcount + 1;
    vgate  <= ~hlast ? vgate  : (vcount == 666-1) ? 1 : (vcount == 600-1) ? 0 : vgate;
    vtype  <= ~hlast ? vtype  : (vcount == 300-1) ? 1 : (vcount == 600-1) ? 0 : vtype;
    vsync  <= ~hlast ? vsync  : (vcount == 637-1) ? 1 : (vcount == 637+6-1) ? 0 : vsync;
    VGA_VSYNCH_N <= vsync;
    count     <= count + (hlast & (vcount == 600-1));
    VGA_Red   <= hgate & vgate & ({vtype,htype^vtype} == count[cbits-1:cbits-2] ? lfsr[0] : {vtype,htype^vtype} == (count[cbits-1:cbits-2] ^ 2'd2) ? lfsr[0] : hcount[5] ^ vcount[5]);
    VGA_Green <= hgate & vgate & ({vtype,htype^vtype} == count[cbits-1:cbits-2] ? lfsr[0] : {vtype,htype^vtype} == (count[cbits-1:cbits-2] ^ 2'd3) ? lfsr[1] : hcount[6] ^ vcount[6]);
    VGA_Blue  <= hgate & vgate & ({vtype,htype^vtype} == count[cbits-1:cbits-2] ? lfsr[0] : 0 ? lfsr[2] : hcount[7] ^ vcount[7]);
  end
endmodule


module top (sys_clk, VGA_Red, VGA_Green, VGA_Blue, VGA_HSYNCH_N, VGA_VSYNCH_N);
  input         sys_clk;
  output        VGA_HSYNCH_N, VGA_VSYNCH_N, VGA_Red, VGA_Green, VGA_Blue;

  vga vga1 (.clk50(sys_clk), .VGA_Red(VGA_Red), .VGA_Green(VGA_Green), .VGA_Blue(VGA_Blue), .VGA_HSYNCH_N(VGA_HSYNCH_N), .VGA_VSYNCH_N(VGA_VSYNCH_N));
endmodule

NET sys_clk      PERIOD = 50 MHz;
NET sys_clk      LOC=T9;
NET VGA_Red      LOC=r12;
NET VGA_Green    LOC=t12;
NET VGA_Blue     LOC=r11;
NET VGA_HSYNCH_N LOC=r9;
NET VGA_VSYNCH_N LOC=t10;