bad lowB corner in Bandgap

Hello
I'm designing a CMOS bandgap circuit and I'm happy to come down to 10mV over most of the Corner simulations (typical is better than 2-3mV).
However, the corners where BJTs are set to Low B the bandgap voltage is more than 70mV over typ corner's and is increasing with higher temperature making my overall performance to about 25mV (worse seperated corner) which is very bad!

Does anyone have a solution to anihilate B-Variation of the BJTs?
biasing... cascading... whatever?

thx for response

Rocko

if beta is low, vbe is higher. when you add a fixed ptat voltage, the total bandgap voltage is higher. there is no trick i know of to compensate for varying vbe (ie varying beta), or else we wouldn't need to trim any of our bandgaps!

so you can consider trimming the gain resistors, or you can investigate whether 70mV of Vbe is really likely - it may be the WC corner, but a fab would have to be in pretty sorry shape to actually give that kind of variation. BTW - what is the beta on that corner? 50 with a typical of 200? my calculations say that 70mv is quite pessimistic in a case like this.

70mV is about 6%. a good figure of merit is about 3% for a quality bandgap, pre-trim. (37mV) but if you're using a standard cell (brokaw, etc) it's just fab variation, and has little to do with your circuit, assuming you know what you're doing and the cell has no boobytraps. i just ran my most recent bandgap from beta of 50 to 250 and it came up as 34mV variation. but on one single wafer we saw 0.6% (7mV) variation, and widest spread from highest lot ever to lowest was about 1.5%.

soooooo - we have to consider whether a beta variation from 50 to 250 is reasonable, or does it mean the fab is allowed to be out of control while they still make you pay for your wafers? if it were me, and we got a lot 6% low, i would send the wafer back and find a fab that can control their diffusions. just me though!

Thanks for your answer,
current gain of bips is really low I noticed (2< beta <10), mabe its 'cause of the "pseudo" vertical bipolar transistor used in CMOS?
I use core-bandgap layout of IEEE Paper " A low supply voltage high PSRR voltage reference in CMOS process" by Khong-Meng Tham and Krishnaswamy Nagaray, which uses a combination of multiple current and bipolar-emiter area.
I will go and try layout from Razavi's Book (Fig 11.35), mabe it performs better in my case...

greetings Rocko

yes, the beta of bjt in cmos is very low.
the best way is trimming

multiplying currents is worse than multiple diodes because now your Vt has a mismatch dependence on mosfets, which is always worse than just using straight mirrors.

I don't understand why the vertical beta is so bad - usually the vertical is pretty good actually, you have to add buried layer to make it that bad.