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How to let VCD wave viewer to display

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fiw0000

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vcd2wlf

all bits of a std_logic_vector signal?

The design is in VHDL. the .vcd file was generated by Modelsim.

When using the vcd wave viewer to view the .vcd file, it can only display 0 bit of all std_logic_vector signals.

What is the problem? Any idea on this?

Thank you
 

modelsim vcd

I tried following code with modelsim version 5.5d on linux x86 platform.
It works perfectly OK! You can try this one on ur end.

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
  
  port (
    clk     : in     std_logic;
    reset_n : in     std_logic;
    count   : buffer std_logic_vector(7 downto 0));

end counter;

architecture behave of counter is

begin  -- behave

  counting: process (clk, reset_n)
  begin  -- process counting
    if reset_n = '0' then               -- asynchronous reset (active low)
      count <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      count <= count + 1;
    end if;
  end process counting;
end behave;

I ran following commands on command promt to compile simulate and generate vcd
file.

vlib work
vcom counter.vhd
vsim -c counter
force -freeze -repeat 10 clk 0 0, 1 5
force -freeze reset_n 0 0, 1 33
vcd file test.vcd
vcd add -r *
run 1000 ns
quit
 

view vcd in modelsim

Hi, nand_gates,
I tried the counter design, but I still couldn't see other bits of the counter than counter(0). The VCD viewer I use is downloaded from **broken link removed**

When using vcd2wlf provided by Modelsim to change the generated vcd to wlf and view it by modelsim, there is no problem with the count signal -- all bits can be displayed.
 

modelsim vcd viewer

Sounds like a bug/issue with WaveVCD tool - why not try GTKWave or just use Modelsim's waveform viewer?

Aji
fiw0000 said:
Hi, nand_gates,
I tried the counter design, but I still couldn't see other bits of the counter than counter(0). The VCD viewer I use is downloaded from h**p://www.iss-us.com/wavevcd/

When using vcd2wlf provided by Modelsim to change the generated vcd to wlf and view it by modelsim, there is no problem with the count signal -- all bits can be displayed.
Click to expand...
 

wave vcd viewer

This seems to be a bug in wave vcd viewer. While dumping modelsim
dumps individual bits of std_logic_vector into vcd dumpfile; which info
wave vcd viewer is not able to understand. You better go for gtkwaves.
 

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