DAC Layout

Hey,
M7 to M3 is pretty far, you can try enhance the layout with shielding the clock's routing with bottom vssa plate(and even side&top shield). I would also see what happens with r-only extraction to examine if it cc issue.

There will always be the G-D coupling of clocks into analog
nodes. Hard switching is worst. Current-steering can be a lot
lower clock-noise input-output bleed-over. But at 3GHz you
may need all the gate drive you can get. Question is where
reducing gate drive stops reducing settling time, or adds
some other error (like, switch no longer looks like a switch
but more of a resistor with variabilities).

A current source DAC where the "switch" is a diff pair that
steers current away or to the summing node, the gate on
the "to" side is static and the control side only swings just
enough to fully steer current, may be the least clock noise
injection.

I agree with the comments above. It could be worth extracting the parts individually, perhaps it's not the "long" clock routing that is an issue but inside the current cell itself. This also gives smaller netlists that are easier to dechiper to find the actual problem.

martinnl said:

I agree with the comments above. It could be worth extracting the parts individually, perhaps it's not the "long" clock routing that is an issue but inside the current cell itself. This also gives smaller netlists that are easier to dechiper to find the actual problem.

Click to expand...

It would certainly be instructive to check how much of the
"noise" is present in ideal unit cells or the whole assembly
without parasitics (aside from those embedded in the FET
compact model) so that you understand the relative
contributions of the various "candidates".

Thank you. for the replies.

@guntherleet
I have added GND shielding on M5/M6. With that, the disturbances on the output reduced from 3mV to 250uV. I do not understand why there are disturbances (~900uV) in the R only extraction? It is also greater than in CC extraction (250uV). Is it the gate to drain coupling that @dick_freebird is talking about? But this disturbance is not observed in the No RC extraction.

@dick_freebird I have used an inverter chain of 3 inverters to reduce the clock coupling to the signals - At the schematic level - no coupling can be seen.
Can you please clarify this - "the gate on the "to" side is static and the control side only swings just enough to fully steer current maybe the least clock noise injection." In a fully differential both the gates turn on/off in the opposite polarity - hence not static. Isn't it?

Also, How to check this - "how much of the "noise" is present in ideal unit cells or the whole assembly without parasitics (aside from those embedded in the FET compact model) so that you understand the relative contributions of the various "candidates"."