yashjain
Junior Member level 1
Hi, Iḿ trying to compare 40 values from a memory array to my input data. If any of those 40 data matches to my input data I go to next state.
I´m using a FOR LOOP for comparing the values in one clock cycle. But it limits my Fmax clock frequency.
How do I write a pipeline based code to check my input data with those 40 values in such a wau that increases my clock frequency?
-> It doesn´t matter if it takes even 40 clock cycles to do the whole thing
Right now the Fmax is 141 MHz
I want to increase it to it max value.
I´m using a FOR LOOP for comparing the values in one clock cycle. But it limits my Fmax clock frequency.
How do I write a pipeline based code to check my input data with those 40 values in such a wau that increases my clock frequency?
-> It doesn´t matter if it takes even 40 clock cycles to do the whole thing
Code:
signal checksum_Y : std_logic_vector(8 downto 0);
signal y_data : std_logic_vector(9 downto 0);
type did_reg is array (0 to did_width-1) of std_logic_vector (9 downto 0); --intiating inferred memory
signal did_arr : did_reg;
when DID_Y =>
checksum_Y <= std_logic_vector(unsigned(y_data(8 downto 0)) + unsigned(checksum_Y)); -- load check sum with previous checksum and current data value
for i in 0 to (did_width) loop -- Loop the did array
if i = did_width then -- If counter reaches the max amount of DID present+1 due to no DID match
curr_state_Y <= IDLE_Y; -- jump tp next state, IDLE_Y
elsif y_data = did_arr(i) then -- check if y_data matches with the element of the did array
mem_arr_Y(count_Y) <= y_data; -- if true, load the data to memeory
count_Y <= count_Y+1; -- increase the memory adress counter
curr_state_Y <= SDID_Y; -- jump to next state, SDID_Y
id_pair_cnt_Y <= i; -- ID pair adrs counter, for SDID pair adrs
exit; -- exit the loop when true
end if;
end loop;
Right now the Fmax is 141 MHz
I want to increase it to it max value.