Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] why the `__FILE__ and `__LINE__ macros not displaying in this SV code ??

Status
Not open for further replies.
A

anilineda

Member level 3
Joined
Mar 10, 2016
Messages
54
Helped
2
Reputation
4
Reaction score
1
Trophy points
8
Activity points
466
Hi, i am a beginner just started learning Systemverilog. while i am trying a small example mentioned in textbooks

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

`include "macro.h" //macro included
class exercise1 ;
  rand bit [3:0] addr;                                    // a simple class
  rand bit [7:0] data;
  constraint cb{addr>2 ; addr < 5 ;}         
endclass
 
module test;
  exercise1 p;                                       // on object created
 
  initial begin
     p=new();                                     // allocated memory space and defaulted to 0.
    `SV_RAND_CHECK(p.randomize());
    $display("next");
    `SV_RAND_CHECK(p.randomize());
    $display("data = %0d, address = %0d", p.data,p.addr);
    `SV_RAND_CHECK(p.randomize());
    $display("data = %0d, address = %0d", p.data,p.addr);
    `SV_RAND_CHECK(p.randomize());
    $display("data = %0d, address = %0d", p.data,p.addr);
    `SV_RAND_CHECK(p.randomize());
    $display("data = %0d, address = %0d", p.data,p.addr);
  end
endmodule
    
// a separate file with the file name "macro.h"
`define SV_RAND_CHECK(r) \
   do begin \
     if ((r)) begin \
       $display("%s:%0d: Randomization passed "%s"", \
                `__FILE__, `__LINE__, r); \
     end \
   end while (0)




result is shown in picture Untitled123.png

- - - Updated - - -

I am mistaken , macros working properly. now the question is argument 'r' is displaying some symbol, but it is supposed to display a true value.
 
Last edited by a moderator:

I don't know SV but this looks wrong:
Code Verilog - [expand]
1

"%s:%0d: Randomization passed "%s""


the "%s:%0d: Randomization passed " ends that string and then you have a %s"" following? Notice the second %s is not pink.

If you wanted double-quotes around the %s then you need to escape them, which I'm not sure if it works when you are already making the `define multi-line with escaped line ends. I'm sort of surprised you didn't get a warning or error when compiling with that display line.
 
  • Like
Reactions: anilineda

    V

    Points: 2
    Helpful Answer Positive Rating
    A

    anilineda

    Points: 2
    Helpful Answer Positive Rating
Your macro should be
Code: 
`define SV_RAND_CHECK(r) \
   begin \
     if ((r)) begin \
       $display("%s:%0d: Randomization passed %b", \
                `__FILE__, `__LINE__, r); \
     end \
   end
 
  • Like
Reactions: anilineda

    V

    Points: 2
    Helpful Answer Positive Rating
    A

    anilineda

    Points: 2
    Helpful Answer Positive Rating
if i use r as like shown `"r`" . what it represents, and the result of this looks big.
`define SV_RAND_CHECK(r) \
do begin \
if ((r)) begin \
$display("%s:%0d: Randomization passed "%h"", \
`__FILE__, `__LINE__, `"r`"); \
end \
end while (0)
Click to expand...

result:
testbench.sv:18: Randomization passed "702e72616e646f6d697a652829"
next
testbench.sv:20: Randomization passed "702e72616e646f6d697a652829"
data = 136, address = 4
testbench.sv:22: Randomization passed "702e72616e646f6d697a652829"
data = 154, address = 4
testbench.sv:24: Randomization passed "702e72616e646f6d697a652829"
data = 95, address = 3
testbench.sv:26: Randomization passed "702e72616e646f6d697a652829"
data = 132, address = 4
 

What do you want to have printed? Do you want the result returned from the call to p.randomize()? This is what you had asked for in the OP. ("but it is supposed to display a true value.") But your last post seems like you want the string representation of what was called. This seems more reasonable; then you want:

Code: 
`define SV_RAND_CHECK(r) \
begin \
if ((r)) begin \
$display("%s:%0d: Randomization passed "%s"", \
`__FILE__, `__LINE__, `"r`"); \
end \
end
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top