Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

45 nm Design rules needed

Status
Not open for further replies.

preneeth772

Newbie level 1
Joined
Sep 24, 2015
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
7
Hi All,

I need min width and min spacing and std cell row height values for 45nm design, anyone plese help me.
 

The design rules depend on which foundry you are following and it varies from foundry to foundry even if you are targetting 45 nm node. Usually foundry will provide a lef file in which all these design rules will be specified.
 

Check the targeted model library......On which you would like to ride............
Like gpdk180, gpdk090, gpdk045...........
Or
Foundry Models like UMC library Or TSMC..........
Read their Manuals carefully......
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top